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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-03-28 19:30:08 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-03-28 19:43:39 -0700 |
| commit | 7f8292335aaf2935dd012be9044d15287e85d318 (patch) | |
| tree | 813de51c60bcaf99062ad1c0878a208d37160c17 /riscv | |
| parent | bdb71e8138085ba81ff01cce2b02f48c7519be1a (diff) | |
| download | spike-7f8292335aaf2935dd012be9044d15287e85d318.zip spike-7f8292335aaf2935dd012be9044d15287e85d318.tar.gz spike-7f8292335aaf2935dd012be9044d15287e85d318.tar.bz2 | |
rvv: fix vmerge[xi] operand use and apply V_CHECK_MASK macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/insns/vmerge_vi.h | 17 | ||||
| -rw-r--r-- | riscv/insns/vmerge_vx.h | 15 |
2 files changed, 11 insertions, 21 deletions
diff --git a/riscv/insns/vmerge_vi.h b/riscv/insns/vmerge_vi.h index 8456770..db76af4 100644 --- a/riscv/insns/vmerge_vi.h +++ b/riscv/insns/vmerge_vi.h @@ -1,26 +1,21 @@ -// vmerge.vi vd, vs2, imm, vm +// vmerge.vi vd, vs2, simm5, vm VI_VI_LOOP ({ bool do_mask = false; - - if (insn.v_vm() == 0) { - int midx = (STATE.VU.vmlen * i) / 32; - int mpos = (STATE.VU.vmlen * i) % 32; - do_mask = (STATE.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; - } + V_CHECK_MASK(do_mask); bool use_first = (insn.v_vm() == 1) || do_mask; switch (STATE.VU.vsew) { case e8: - STATE.VU.elt<uint8_t>(rd_num, i) = use_first ? rs1 : vs2; + STATE.VU.elt<uint8_t>(rd_num, i) = use_first ? simm5 : vs2; break; case e16: - STATE.VU.elt<uint16_t>(rd_num, i) = use_first ? rs1 : vs2; + STATE.VU.elt<uint16_t>(rd_num, i) = use_first ? simm5 : vs2; break; case e32: - STATE.VU.elt<uint32_t>(rd_num, i) = use_first ? rs1 : vs2; + STATE.VU.elt<uint32_t>(rd_num, i) = use_first ? simm5 : vs2; break; default: - STATE.VU.elt<uint64_t>(rd_num, i) = use_first ? rs1 : vs2; + STATE.VU.elt<uint64_t>(rd_num, i) = use_first ? simm5 : vs2; } }) diff --git a/riscv/insns/vmerge_vx.h b/riscv/insns/vmerge_vx.h index efb34dd..fd363bb 100644 --- a/riscv/insns/vmerge_vx.h +++ b/riscv/insns/vmerge_vx.h @@ -2,25 +2,20 @@ VI_VX_LOOP ({ bool do_mask = false; - - if (insn.v_vm() == 0) { - int midx = (STATE.VU.vmlen * i) / 32; - int mpos = (STATE.VU.vmlen * i) % 32; - do_mask = (STATE.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; - } + V_CHECK_MASK(do_mask); bool use_first = (insn.v_vm() == 1) || do_mask; switch (STATE.VU.vsew) { case e8: - STATE.VU.elt<uint8_t>(rd_num, i) = use_first ? simm5 : vs2; + STATE.VU.elt<uint8_t>(rd_num, i) = use_first ? rs1 : vs2; break; case e16: - STATE.VU.elt<uint16_t>(rd_num, i) = use_first ? simm5 : vs2; + STATE.VU.elt<uint16_t>(rd_num, i) = use_first ? rs1 : vs2; break; case e32: - STATE.VU.elt<uint32_t>(rd_num, i) = use_first ? simm5 : vs2; + STATE.VU.elt<uint32_t>(rd_num, i) = use_first ? rs1 : vs2; break; default: - STATE.VU.elt<uint64_t>(rd_num, i) = use_first ? simm5 : vs2; + STATE.VU.elt<uint64_t>(rd_num, i) = use_first ? rs1 : vs2; } }) |