rvv: Fixed the following instructions. Based on the new macros

     vadd_v[vxi]
     vand_v[vx]
     vor_vx
     vxor_vx
     vsll_v[vxi]
     vsra_v[vxi]
     vsrl_v[vxi]

15 files changed, 15 insertions, 15 deletions

diff --git a/riscv/insns/vadd_vi.h b/riscv/insns/vadd_vi.h
index b87d427..d260809 100644
--- a/riscv/insns/vadd_vi.h
+++ b/riscv/insns/vadd_vi.h
@@ -1,5 +1,5 @@
 // vadd.vi vd, simm5, vs2, vm
 VI_VI_LOOP
 ({
-    vd = sext_xlen(simm5 + vs2);
+    vd = vsext(simm5 + vs2, sew);
  })
diff --git a/riscv/insns/vand_vi.h b/riscv/insns/vand_vi.h
index a8df2eb..84f90e1 100644
--- a/riscv/insns/vand_vi.h
+++ b/riscv/insns/vand_vi.h
@@ -1,5 +1,5 @@
 // vand.vi vd, simm5, vs2, vm
 VI_VI_LOOP
 ({
-    vd = sext_xlen(simm5 & vs2);
+    vd = vsext(simm5 & vs2, sew);
  })
diff --git a/riscv/insns/vand_vv.h b/riscv/insns/vand_vv.h
index 49ac079..dad16e1 100644
--- a/riscv/insns/vand_vv.h
+++ b/riscv/insns/vand_vv.h
@@ -1,5 +1,5 @@
 // vand.vv vd, vs1, vs2, vm
 VI_VV_LOOP
 ({
-    vd = sext_xlen(vs1 & vs2);
+    vd = vsext(vs1 & vs2, sew);
  })
diff --git a/riscv/insns/vand_vx.h b/riscv/insns/vand_vx.h
index be772d6..a3294e4 100644
--- a/riscv/insns/vand_vx.h
+++ b/riscv/insns/vand_vx.h
@@ -1,5 +1,5 @@
 // vand.vx vd, rs1, vs2, vm
 VI_VX_LOOP
 ({
-    vd = sext_xlen(rs1 & vs2);
+    vd = vsext(rs1 & vs2, sew);
  })
diff --git a/riscv/insns/vor_vx.h b/riscv/insns/vor_vx.h
index e96b7b6..ab089ad 100644
--- a/riscv/insns/vor_vx.h
+++ b/riscv/insns/vor_vx.h
@@ -1,5 +1,5 @@
 // vor
 VI_VX_LOOP
 ({
-    vd = sext_xlen(rs1 | vs2);
+    vd = vsext(rs1 | vs2, sew);
 })
diff --git a/riscv/insns/vsll_vi.h b/riscv/insns/vsll_vi.h
index 6bd49c7..9756bed 100644
--- a/riscv/insns/vsll_vi.h
+++ b/riscv/insns/vsll_vi.h
@@ -1,5 +1,5 @@
 // vsll
 VI_VI_LOOP
 ({
-    WRITE_RD(sext_xlen(simm5 << (vs2 & (xlen-1))));
+    vd = vsext(vs2 << (simm5 & (sew - 1)), sew);
 })
diff --git a/riscv/insns/vsll_vv.h b/riscv/insns/vsll_vv.h
index 30151f7..2fb7835 100644
--- a/riscv/insns/vsll_vv.h
+++ b/riscv/insns/vsll_vv.h
@@ -1,5 +1,5 @@
 // vsll
 VI_VV_LOOP
 ({
-    WRITE_RD(sext_xlen(vs1 << (vs2 & (xlen-1))));
+    vd = vsext(vs2 << (vs1 & (sew - 1)), sew);
 })
diff --git a/riscv/insns/vsll_vx.h b/riscv/insns/vsll_vx.h
index d87c92e..abbb3d3 100644
--- a/riscv/insns/vsll_vx.h
+++ b/riscv/insns/vsll_vx.h
@@ -1,5 +1,5 @@
 // vsll
 VI_VX_LOOP
 ({
-    WRITE_RD(sext_xlen(rs1 << (vs2 & (xlen-1))));
+    vd = vsext(vs2 << (rs1 & (sew-1)), sew);
 })
diff --git a/riscv/insns/vsra_vi.h b/riscv/insns/vsra_vi.h
index 3dcc3ea..6e03b35 100644
--- a/riscv/insns/vsra_vi.h
+++ b/riscv/insns/vsra_vi.h
@@ -1,5 +1,5 @@
 // vsra
 VI_VI_LOOP
 ({
-    WRITE_RD(sext_xlen(sext_xlen(simm5) >> (vs2 & (xlen-1))));
+    vd = vsext(vs2 >> (simm5 & (sew - 1)), sew);
 })
diff --git a/riscv/insns/vsra_vv.h b/riscv/insns/vsra_vv.h
index cccdb58..eef7714 100644
--- a/riscv/insns/vsra_vv.h
+++ b/riscv/insns/vsra_vv.h
@@ -1,5 +1,5 @@
 // vsra
 VI_VV_LOOP
 ({
-    WRITE_RD(sext_xlen(sext_xlen(vs1) >> (vs2 & (xlen-1))));
+    vd = vsext(vs2 >> (vs1 & (sew - 1)), sew);
 })
diff --git a/riscv/insns/vsra_vx.h b/riscv/insns/vsra_vx.h
index 8b1b639..d465372 100644
--- a/riscv/insns/vsra_vx.h
+++ b/riscv/insns/vsra_vx.h
@@ -1,5 +1,5 @@
 // vsra
 VI_VX_LOOP
 ({
-    WRITE_RD(sext_xlen(sext_xlen(rs1) >> (vs2 & (xlen-1))));
+    vd = vsext(vs2 >> (rs1 & (sew - 1)), sew);
 })
diff --git a/riscv/insns/vsrl_vi.h b/riscv/insns/vsrl_vi.h
index 5651948..c9a8974 100644
--- a/riscv/insns/vsrl_vi.h
+++ b/riscv/insns/vsrl_vi.h
@@ -1,5 +1,5 @@
 // vsrl
 VI_VI_LOOP
 ({
-    WRITE_RD(sext_xlen(zext_xlen(simm5) >> (vs2 & (xlen-1))));
+    vd = vzext(vs2 >> (simm5 & (sew - 1)), sew);
 })
diff --git a/riscv/insns/vsrl_vv.h b/riscv/insns/vsrl_vv.h
index f2a0683..fa3ca8d 100644
--- a/riscv/insns/vsrl_vv.h
+++ b/riscv/insns/vsrl_vv.h
@@ -1,5 +1,5 @@
 // vsrl
 VI_VV_LOOP
 ({
-    WRITE_RD(sext_xlen(zext_xlen(vs1) >> (vs2 & (xlen-1))));
+    vd = vzext(vs2 >> (vs1 & (sew - 1)), sew);
 })
diff --git a/riscv/insns/vsrl_vx.h b/riscv/insns/vsrl_vx.h
index b3717c7..f1eeed9 100644
--- a/riscv/insns/vsrl_vx.h
+++ b/riscv/insns/vsrl_vx.h
@@ -1,5 +1,5 @@
 // vsrl
 VI_VX_LOOP
 ({
-    // NOT IMPLEMENTED YET
+    vd = vzext(vs2 >> (rs1 & (sew - 1)), sew);
 })
diff --git a/riscv/insns/vxor_vx.h b/riscv/insns/vxor_vx.h
index b29c0e8..427de78 100644
--- a/riscv/insns/vxor_vx.h
+++ b/riscv/insns/vxor_vx.h
@@ -1,5 +1,5 @@
 // vxor
 VI_VX_LOOP
 ({
-    vd = sext_xlen(rs1 ^ vs2);
+    vd = vsext(rs1 ^ vs2, sew);
 })