processor: for rounding mode and config access functions

2 files changed, 29 insertions, 0 deletions

diff --git a/riscv/processor.cc b/riscv/processor.cc
index be91a7e..ba47568 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -160,6 +160,14 @@ reg_t vectorUnit_t::setVL(uint64_t regId, reg_t reqVL, reg_t newType){
   return vl;
 }
 
+void vectorUnit_t::set_vcsr(int which, reg_t val){
+
+}
+
+reg_t vectorUnit_t::get_vcsr(int which){
+	return 0;
+}
+
 void processor_t::set_debug(bool value)
 {
   debug = value;
diff --git a/riscv/processor.h b/riscv/processor.h
index 46c7e76..f78cba7 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -88,6 +88,14 @@ inline reg_t BITS(reg_t v, int hi, int lo){
   return (v >> lo) & ((2 << (hi - lo)) - 1);
 }
 
+enum VRM{
+	RUN = 0,
+	RNE,
+	RDN,
+	ROD,
+	INVALID_RM
+};
+
 struct vectorUnit_t {
   void *reg_file;
   char reg_referenced[NVPR];  
@@ -125,6 +133,19 @@ struct vectorUnit_t {
     free(reg_file);
     reg_file = 0;
   }
+
+  void set_vcsr(int which, reg_t val);
+  reg_t get_vcsr(int which);
+
+  reg_t get_vlen() { return VLEN; }
+  reg_t get_elen() { return ELEN; }
+  reg_t get_slen() { return SLEN; }
+
+  VRM get_vround_mode() {
+	  uint32_t rm = BITS(vxrm, 0, 2);
+	  assert( rm < VRM::INVALID_RM );
+	  return (VRM)rm;
+  }
 };
 
 struct prev_reg_state_t {