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author | Dave.Wen <dave.wen@sifive.com> | 2019-03-31 08:01:18 -0700 |
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committer | Dave.Wen <dave.wen@sifive.com> | 2019-03-31 22:31:09 -0700 |
commit | 42b93deb85e314ed13730a6e096fef0198a3dcbe (patch) | |
tree | 53e7b6803e24ff97a03711e07b2c7e91844cc3e6 /riscv | |
parent | ccec7acbdeb52efb1777d35f63ca073fe607d3f9 (diff) | |
download | spike-42b93deb85e314ed13730a6e096fef0198a3dcbe.zip spike-42b93deb85e314ed13730a6e096fef0198a3dcbe.tar.gz spike-42b93deb85e314ed13730a6e096fef0198a3dcbe.tar.bz2 |
rvv: rewrite the vector destination for varies sew
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/decode.h | 32 | ||||
-rw-r--r-- | riscv/processor.h | 27 |
2 files changed, 55 insertions, 4 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 611344c..d360e91 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -380,12 +380,36 @@ inline long double to_f(float128_t f){long double r; memcpy(&r, &f, sizeof(r)); } \ STATE.VU.vstart = 0; +#define VV_PARAMS(x) \ + type_sew_t<x>::type &vd = STATE.VU.elt<type_sew_t<x>::type>(rd_num, i); \ + type_sew_t<x>::type vs1 = STATE.VU.elt<type_sew_t<x>::type>(rs1_num, i); \ + type_sew_t<x>::type vs2 = STATE.VU.elt<type_sew_t<x>::type>(rs2_num, i); \ + +#define VX_PARAMS(x) \ + type_sew_t<x>::type &vd = STATE.VU.elt<type_sew_t<x>::type>(rd_num, i); \ + type_sew_t<x>::type rs1 = RS1; \ + type_sew_t<x>::type vs2 = STATE.VU.elt<type_sew_t<x>::type>(rs2_num, i); \ + +#define VI_PARAMS(x) \ + type_sew_t<x>::type &vd = STATE.VU.elt<type_sew_t<x>::type>(rd_num, i); \ + type_sew_t<x>::type simm5 = (((int8_t)rs1_num) << 3) >> 3; \ + type_sew_t<x>::type vs2 = STATE.VU.elt<type_sew_t<x>::type>(rs2_num, i); \ + #define VI_VV_LOOP(BODY) \ VI_LOOP_BASE \ - int32_t &vd = STATE.VU.elt<int32_t>(rd_num, i); \ - int32_t vs1 = STATE.VU.elt<int32_t>(rs1_num, i); \ - int32_t vs2 = STATE.VU.elt<int32_t>(rs2_num, i); \ - BODY; \ + if (sew == 8){ \ + VV_PARAMS(8); \ + BODY; \ + }else if(sew == 16){ \ + VV_PARAMS(16); \ + BODY; \ + }else if(sew == 32){ \ + VV_PARAMS(32); \ + BODY; \ + }else if(sew == 64){ \ + VV_PARAMS(64); \ + BODY; \ + } \ VI_LOOP_END #define VI_VI_LOOP(BODY) \ diff --git a/riscv/processor.h b/riscv/processor.h index f78cba7..538f873 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -96,6 +96,33 @@ enum VRM{ INVALID_RM }; +template<uint64_t N> +struct type_sew_t; + +template<> +struct type_sew_t<8> +{ + using type=int8_t; +}; + +template<> +struct type_sew_t<16> +{ + using type=int16_t; +}; + +template<> +struct type_sew_t<32> +{ + using type=int32_t; +}; + +template<> +struct type_sew_t<64> +{ + using type=int64_t; +}; + struct vectorUnit_t { void *reg_file; char reg_referenced[NVPR]; |