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2020-05-19rvv: fix widen checkingChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-17rvv: mlen=1 WIPDave.Wen1-1/+1
2020-05-14rvv: fix the fractional lmulDave.Wen1-7/+18
2020-05-13rvv: amo pre-0.9Chih-Min Chao1-0/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: fractional_lmul when lmul < 1Dave.Wen1-2/+10
2020-05-13vtype: fix the vta and vma functions and debugging displayDave.Wen1-1/+1
2020-05-07rvv: add eew and lmul for vle/vse/vleffDave.Wen1-4/+8
2020-04-29zfh: zfh require F extension supportChih-Min Chao1-0/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-27rvv: align VCSR with upstreamChih-Min Chao1-11/+9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-27parse: refine error format reportingChih-Min Chao1-10/+24
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14parser: extend --isa to support extended extensionChih-Min Chao1-16/+40
1. support extened extension ex: --isa="imadc_zvamo_zvqmac 2. relax extenion character order --isa=imadc or --isa==cdima 3. use another bit structure to keep all supported extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: add new vcsr vector csrChih-Min Chao1-15/+25
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-10op: update CSRChih-Min Chao1-4/+4
1. add new hypervisor csr 2. add debug module csr 3. add some new high part register for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-05option: flag x extension without loading shared lib (#439)Chih-Min Chao1-1/+5
reserve the word 'dummy' to set the x-extension in misa but not to load a related shared library. ex: --isa=IMACXdummy Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-05Deny hart access to debug CSRs when not in D-modeAndrew Waterman1-0/+8
Follow-on to 1ef875316adee8174fe2cf83317f59019d3c1aa2 cc @timsifive
2020-04-05Write execution logs to a named log file (#409)Rupert Swarbrick1-16/+12
This patch adds a --log argument to spike. If not given, the behaviour is unchanged: messages logging execution of instructions and (if commit logging is enabled) commits go to stderr. If --log=P is given, Spike now writes these messages to a log file at the path P. This is nice, because they are no longer tangled up with other errors and warnings. The code is mostly plumbing: passing a FILE* object through to the functions that were using stderr. I've written a simple "log_file_t" class, which opens a log file if necessary and yields it or stderr.
2020-03-26rvv: check vlen == slenChih-Min Chao1-0/+2
For current implementation, vlen must be equal to slen. It will be added in the future. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-23rvv: fix WARL behavior for vxsat and vxrmChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-08Don't clobber trigger types when initializing stateAndrew Waterman1-1/+1
2020-03-05rvv: fix vf(w)redsum option parsing bugZhen Wei1-4/+5
Fix the bug that Spike aborted when fredsum option is not specified even those test cases are not involved in vf(w)redsum.
2020-03-05rvv: avoid redundant std::string comparisonZhen Wei1-6/+8
2020-03-05rvv: import parallel vf(w)redsum hardware impl.Zhen Wei1-2/+15
The number of vector FP ALUs and implementations of vf(w)redsum could be passed as options by the following example: "--varch=vlen:512,elen:32,slen:512,nalu:4,fredsum-impl:parallel" By default, 4 of vector FP ALUs and ordered vector FP reduction sum implementations are assumed.
2020-03-03Add do-nothing support for mcountinhibit CSRRupert Swarbrick1-0/+1
This CSR appeared in version 1.11 of the ISA and is described in the Volume II: Privileged Architecture manual. It's an optional register and should read as zero if not implemented, which is what this patch does.
2020-03-03Check presence of [S|U] extension for mstatus.[sxl|uxl] read/writeUdit Khanna1-7/+8
2020-03-03Initialize some uninitialized stateAndrew Waterman1-0/+2
2020-03-04rvv: remove the option of vector impl. checkZhen Wei1-766/+0
The check is not needed anymore since most vector kernels are supported in current implemented vector instruction set.
2020-02-27rvv: enable --varch to parse string type optionsZhen Wei1-30/+42
To improve the readability of varch argument, the format of options within varch are changed from "v128:e64:s512" to "vlen:128,elen:64,slen:512".
2020-02-19Improve --varch error checking. (#394)Tim Newsome1-8/+18
* Improve --varch error checking. Print out why an option has problems. Add check that elen must be >= xlen, flen, per the spec. Since RV32G includes D by default, bump default elen to 64. * Remove debug printf.
2020-02-12Fix pmpcfg0 initial value regression from ↵Andrew Waterman1-5/+5
cb254bfab5fbb6d69e5dd336798861e7c1183e52
2020-02-12Initialize PMPs with set_csr to fix WARLness of initial valueAndrew Waterman1-3/+6
2020-02-12Prevent pmpaddr* and satp from holding invalid physical addressesAndrew Waterman1-2/+3
Resolves #386
2020-02-12rvv: remove duplicate vectorUnit declarationChih-Min Chao1-2/+3
forget to remove the vectorUnit outside, which has been moved into proccess_t as inner class Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12commitlog: rvv: change vector register read/write interfaceChih-Min Chao1-2/+2
1. add an extra argument to support commitlog 2. move vectorUnit_t into processor_t to avoid circular dependency hell Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12commitlog: extend reg record to keep multiple accesssChih-Min Chao1-1/+1
1. use hash to keep duplicated register write since vector has lmul feature 2. enhance print fuction to support type larger than 64bit Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12commitlog: extend load/store record to keep multiple accessChih-Min Chao1-2/+2
use vector to store memory accesses Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12state: rewrite state_t initializationChih-Min Chao1-5/+51
implement a specific initalization function to avoid weird segfault when the member is complex structure such as map or hash. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12Expose sstatus.vs fieldAndrew Waterman1-0/+1
2020-02-11rvv: fix Vxrm not reflected in fcsr (1763)Dave.Wen1-2/+7
2019-12-19Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)Udit Khanna1-1/+2
* SFENCE.VMA requires S-mode * MSTATUS.SUM hardwired to 0 if no S-Mode
2019-12-12rvv: fine sstatus.vs checkingChih-Min Chao1-9/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-12-02Fix (benign) uninitialized variableAndrew Waterman1-1/+1
2019-12-02Initialize state.misa prior to calls to supports_extensionAndrew Waterman1-0/+2
Partially reverts 0162a6e72421b5cbec1905b4cae7bfab98afe83f Closes #361
2019-12-02rvv: make state diryt when csr is writtenChih-Min Chao1-0/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-12-02rvv: support new mstatus.vs field defined in v0.8Chih-Min Chao1-3/+10
mstatus.vs is similiar to mstatus.fs and used to contoller the state of vector unit. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: change vsetvl[i] to match 0.8 specChih-Min Chao1-5/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: replace vn suffic by 'w'Chih-Min Chao1-24/+24
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-10/+11
1. vfncvt*.v -> vfncvt*.w 2. add vfncvt.rod.f.f.w Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: add read-only vleb csrChih-Min Chao1-0/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: add quad insn and new vlenb csrChih-Min Chao1-14/+14
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-18rvv: remove rest of vaadd_viChih-Min Chao1-2/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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