diff options
| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-19 11:26:21 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-19 11:26:21 -0700 |
| commit | 3a17237fd605094f33c036900e5a638aa941b2e1 (patch) | |
| tree | adcba1a25a2fc0689095fa5bc7f46b799ae156fe /riscv/processor.cc | |
| parent | cba9c9d7c95219c7fc7c55c85f8ab0d31d9b9d78 (diff) | |
| download | spike-3a17237fd605094f33c036900e5a638aa941b2e1.zip spike-3a17237fd605094f33c036900e5a638aa941b2e1.tar.gz spike-3a17237fd605094f33c036900e5a638aa941b2e1.tar.bz2 | |
rvv: fix widen checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 01a8021..d64335f 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -404,6 +404,7 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT } else { vlmul = 1 << vlmul; vlmax = VLEN/vsew * vlmul; + vflmul = vlmul; } vmlen = 1; |