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| author | Andrew Waterman <andrew@sifive.com> | 2020-01-30 00:28:11 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-12 23:08:01 -0800 |
| commit | 496b58190c11af44849d12886a610c36d7737f5a (patch) | |
| tree | cc0c08c701d791ef40360f739f14c78cc35b6534 /riscv/processor.cc | |
| parent | 5048b7b34db49c59340dd80c6188a6a5c2b18dc3 (diff) | |
| download | spike-496b58190c11af44849d12886a610c36d7737f5a.zip spike-496b58190c11af44849d12886a610c36d7737f5a.tar.gz spike-496b58190c11af44849d12886a610c36d7737f5a.tar.bz2 | |
Fix pmpcfg0 initial value regression from cb254bfab5fbb6d69e5dd336798861e7c1183e52
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 1470b13..dff4db4 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1115,16 +1115,16 @@ void processor_t::reset() { state.reset(max_isa); - // For backwards compatibility with software that is unaware of PMP, - // initialize PMP to permit unprivileged access to all of memory. - set_csr(CSR_PMPADDR0, ~reg_t(0)); - set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT); - state.dcsr.halt = halt_on_reset; halt_on_reset = false; set_csr(CSR_MSTATUS, state.mstatus); VU.reset(); + // For backwards compatibility with software that is unaware of PMP, + // initialize PMP to permit unprivileged access to all of memory. + set_csr(CSR_PMPADDR0, ~reg_t(0)); + set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT); + if (ext) ext->reset(); // reset the extension |