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authorAndrew Waterman <andrew@sifive.com>2020-01-24 13:31:59 -0800
committerChih-Min Chao <chihmin.chao@sifive.com>2020-02-12 23:08:01 -0800
commit0f092a4e24cc54d6b1c9c807942e9cd14b9e0f28 (patch)
treea42594719771d2f51397d3b55ee5ad3f843fa35e /riscv/processor.cc
parent48e08c866979d229bc23af69d720a0d2ce632df8 (diff)
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Prevent pmpaddr* and satp from holding invalid physical addresses
Resolves #386
Diffstat (limited to 'riscv/processor.cc')
-rw-r--r--riscv/processor.cc5
1 files changed, 3 insertions, 2 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index cc7d249..b6f3d85 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -1314,7 +1314,7 @@ void processor_t::set_csr(int which, reg_t val)
bool next_locked = i+1 < state.n_pmp && (state.pmpcfg[i+1] & PMP_L);
bool next_tor = i+1 < state.n_pmp && (state.pmpcfg[i+1] & PMP_A) == PMP_TOR;
if (!locked && !(next_locked && next_tor))
- state.pmpaddr[i] = val;
+ state.pmpaddr[i] = val & ((reg_t(1) << (MAX_PADDR_BITS - PMP_SHIFT)) - 1);
mmu->flush_tlb();
}
@@ -1447,13 +1447,14 @@ void processor_t::set_csr(int which, reg_t val)
return set_csr(CSR_MIE,
(state.mie & ~state.mideleg) | (val & state.mideleg));
case CSR_SATP: {
+ reg_t rv64_ppn_mask = (reg_t(1) << (MAX_PADDR_BITS - PGSHIFT)) - 1;
mmu->flush_tlb();
if (max_xlen == 32)
state.satp = val & (SATP32_PPN | SATP32_MODE);
if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
get_field(val, SATP64_MODE) == SATP_MODE_SV48))
- state.satp = val & (SATP64_PPN | SATP64_MODE);
+ state.satp = val & (SATP64_PPN | SATP64_MODE | rv64_ppn_mask);
break;
}
case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;