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| author | Andrew Waterman <andrew@sifive.com> | 2020-01-13 12:08:47 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-12 23:08:01 -0800 |
| commit | f2fc51e27bdb1a73f082e6bb2bdc53c47b1be02e (patch) | |
| tree | 6d8a1faf3cc403a825e3a9dba170b6d30ab16d4f /riscv/processor.cc | |
| parent | b7a05a6ba257cf42cb2179f78d14608c9eb23546 (diff) | |
| download | spike-f2fc51e27bdb1a73f082e6bb2bdc53c47b1be02e.zip spike-f2fc51e27bdb1a73f082e6bb2bdc53c47b1be02e.tar.gz spike-f2fc51e27bdb1a73f082e6bb2bdc53c47b1be02e.tar.bz2 | |
Expose sstatus.vs field
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index b797ae6..df13bca 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1592,6 +1592,7 @@ reg_t processor_t::get_csr(int which) case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS + | (supports_extension('V') ? SSTATUS_VS : 0) | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS || |