rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-05-19	rvv: fix widen checking	Chih-Min Chao	1	-0/+1
2020-05-17	rvv: mlen=1 WIP	Dave.Wen	1	-1/+1
2020-05-14	rvv: fix the fractional lmul	Dave.Wen	1	-7/+18
2020-05-13	rvv: amo pre-0.9	Chih-Min Chao	1	-0/+5
2020-05-13	rvv: fractional_lmul when lmul < 1	Dave.Wen	1	-2/+10
2020-05-13	vtype: fix the vta and vma functions and debugging display	Dave.Wen	1	-1/+1
2020-05-07	rvv: add eew and lmul for vle/vse/vleff	Dave.Wen	1	-4/+8
2020-04-29	zfh: zfh require F extension support	Chih-Min Chao	1	-0/+3
2020-04-27	rvv: align VCSR with upstream	Chih-Min Chao	1	-11/+9
2020-04-27	parse: refine error format reporting	Chih-Min Chao	1	-10/+24
2020-04-14	parser: extend --isa to support extended extension	Chih-Min Chao	1	-16/+40
2020-04-14	rvv: add new vcsr vector csr	Chih-Min Chao	1	-15/+25
2020-04-10	op: update CSR	Chih-Min Chao	1	-4/+4
2020-04-05	option: flag x extension without loading shared lib (#439)	Chih-Min Chao	1	-1/+5
2020-04-05	Deny hart access to debug CSRs when not in D-mode	Andrew Waterman	1	-0/+8
2020-04-05	Write execution logs to a named log file (#409)	Rupert Swarbrick	1	-16/+12
2020-03-26	rvv: check vlen == slen	Chih-Min Chao	1	-0/+2
2020-03-23	rvv: fix WARL behavior for vxsat and vxrm	Chih-Min Chao	1	-2/+2
2020-03-08	Don't clobber trigger types when initializing state	Andrew Waterman	1	-1/+1
2020-03-05	rvv: fix vf(w)redsum option parsing bug	Zhen Wei	1	-4/+5
2020-03-05	rvv: avoid redundant std::string comparison	Zhen Wei	1	-6/+8
2020-03-05	rvv: import parallel vf(w)redsum hardware impl.	Zhen Wei	1	-2/+15
2020-03-03	Add do-nothing support for mcountinhibit CSR	Rupert Swarbrick	1	-0/+1
2020-03-03	Check presence of [S\|U] extension for mstatus.[sxl\|uxl] read/write	Udit Khanna	1	-7/+8
2020-03-03	Initialize some uninitialized state	Andrew Waterman	1	-0/+2
2020-03-04	rvv: remove the option of vector impl. check	Zhen Wei	1	-766/+0
2020-02-27	rvv: enable --varch to parse string type options	Zhen Wei	1	-30/+42
2020-02-19	Improve --varch error checking. (#394)	Tim Newsome	1	-8/+18
2020-02-12	Fix pmpcfg0 initial value regression from cb254bfab5fbb6d69e5dd336798861e7c11...	Andrew Waterman	1	-5/+5
2020-02-12	Initialize PMPs with set_csr to fix WARLness of initial value	Andrew Waterman	1	-3/+6
2020-02-12	Prevent pmpaddr* and satp from holding invalid physical addresses	Andrew Waterman	1	-2/+3
2020-02-12	rvv: remove duplicate vectorUnit declaration	Chih-Min Chao	1	-2/+3
2020-02-12	commitlog: rvv: change vector register read/write interface	Chih-Min Chao	1	-2/+2
2020-02-12	commitlog: extend reg record to keep multiple accesss	Chih-Min Chao	1	-1/+1
2020-02-12	commitlog: extend load/store record to keep multiple access	Chih-Min Chao	1	-2/+2
2020-02-12	state: rewrite state_t initialization	Chih-Min Chao	1	-5/+51
2020-02-12	Expose sstatus.vs field	Andrew Waterman	1	-0/+1
2020-02-11	rvv: fix Vxrm not reflected in fcsr (1763)	Dave.Wen	1	-2/+7
2019-12-19	Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)	Udit Khanna	1	-1/+2
2019-12-12	rvv: fine sstatus.vs checking	Chih-Min Chao	1	-9/+2
2019-12-02	Fix (benign) uninitialized variable	Andrew Waterman	1	-1/+1
2019-12-02	Initialize state.misa prior to calls to supports_extension	Andrew Waterman	1	-0/+2
2019-12-02	rvv: make state diryt when csr is written	Chih-Min Chao	1	-0/+3
2019-12-02	rvv: support new mstatus.vs field defined in v0.8	Chih-Min Chao	1	-3/+10
2019-11-27	rvv: change vsetvl[i] to match 0.8 spec	Chih-Min Chao	1	-5/+5
2019-11-27	rvv: replace vn suffic by 'w'	Chih-Min Chao	1	-24/+24
2019-11-27	rvv: rename vfncvt suffix and add rod rouding type	Chih-Min Chao	1	-10/+11
2019-11-27	rvv: add read-only vleb csr	Chih-Min Chao	1	-0/+6
2019-11-27	rvv: add quad insn and new vlenb csr	Chih-Min Chao	1	-14/+14
2019-11-18	rvv: remove rest of vaadd_vi	Chih-Min Chao	1	-2/+0