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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-19 23:16:48 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-23 20:58:29 -0700 |
| commit | e3286f0e85ead74026f1b95451a5d7cd3c9cc549 (patch) | |
| tree | 8977b323492891205298adedda02de655898a582 /riscv/processor.cc | |
| parent | 7d50fc53b2d20212e19e226b9e9b45979eb0db73 (diff) | |
| download | spike-e3286f0e85ead74026f1b95451a5d7cd3c9cc549.zip spike-e3286f0e85ead74026f1b95451a5d7cd3c9cc549.tar.gz spike-e3286f0e85ead74026f1b95451a5d7cd3c9cc549.tar.bz2 | |
rvv: fix WARL behavior for vxsat and vxrm
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 3a0679d..02d2269 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -828,11 +828,11 @@ void processor_t::set_csr(int which, reg_t val) break; case CSR_VXSAT: dirty_fp_state; - VU.vxsat = val; + VU.vxsat = val & 0x1ul; break; case CSR_VXRM: dirty_fp_state; - VU.vxrm = val; + VU.vxrm = val & 0x3ul; break; } } |