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6 daysSupport APX CFCMOVCui, Lili1-0/+5
The CMOVcc instruction proposed by EVEX has four different forms, corresponding to the four possible combinations of EVEX.ND and EVEX.NF values. In the encoder part, when the CFCMOV template supports EVEX_NF, it means that it requires EVEX.NF to be 1. In the decoder part, CFCMOV_Fixup is used to reverse source and destination operands in the 2-operand case. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Set NF bit for cfcmov when the insn template supports EVEX_NF. * testsuite/gas/i386/x86-64-apx-inval.l: Add invalid tests for cfcmov. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add tests for cfcmov and cmov. * testsuite/gas/i386/x86-64-apx-cfcmov-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add cfcmov instructions. * i386-dis.c (CFCMOV_Fixup): Special handling of cfcmov. (putop): Print 'cf' for cfcmov instructions. * i386-opc.h (EVEX_NF): New. * i386-opc.tbl: Add cfcmov instructions. * i386-mnem.h: Regerated. * i386-tbl.h: Regerated.
12 daysx86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich1-1/+4
With both sources being registers, these insns are almost commutative; the only extra adjustment needed is inversion of the encoded condition.
12 daysx86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich1-2/+2
The same properties apply there.
12 daysx86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich1-6/+6
..., for differing only in the resulting EFLAGS, which are left untouched anyway. That's a shorter encoding, available as long as certain constraints on operands are met; see code comments. (SHL-by-1 forms may then be subject to further optimization that was introduced earlier.) Note that kind of as a side effect this also converts multiplication by 1 to shift by 0, which is a plain move or even no-op anyway. That could be further shrunk (as could be presence of shifts/rotates by 0 in the original code as well as a fair set of other {nf}-form insns), yet the expectation (for now) is that people won't write such code in the first place.
12 daysx86/APX: optimize certain {nf}-form insns to LEAJan Beulich1-3/+3
..., as that leaves EFLAGS untouched anyway. That's a shorter encoding, available as long as certain constraints on operand size and registers are met; see code comments. Note that this requires deferring to derive encoding_evex from {nf} presence, as in optimize_encoding() we want to avoid touching the insns when {evex} was also used. Note further that this requires want_disp32() to now also consider the opcode: We don't want to replace i.tm.mnem_off, for diagnostics to still report the original mnemonic (or else things can get confusing). While there, correct adjacent mis-indentation.
12 daysx86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich1-11/+11
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS.CF, for the NF variants the immediate can be got rid of in that case by switching to a 1-bit rotate in the opposite direction.
12 daysx86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich1-12/+12
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS, for the NF variants we can safely replace ones using 0x80 by the respectively other insn while negating the immediate, saving 3 immediate bytes (just 1 though for 16-bit operand size). Similarly we can replace ones using 1 / -1 by INC/DEC (eliminating the immediate).
2024-06-21x86: optimize {,V}PEXTR{D,Q} with immediate of 0Jan Beulich1-6/+6
Such are equivalent to simple moves, which are up to 3 bytes shorter to encode (and perhaps also cheaper to execute).
2024-06-21x86: optimize left-shift-by-1Jan Beulich1-28/+28
These can be replaced by adds when acting on a register operand. While for the scalar forms there's no gain in encoding size, ADD generally has higher throughput than SHL. EFLAGS set by ADD are a superset of those set by SHL (AF in particular is undefined there). For the SIMD cases the transformation also reduced code size, by eliminating the 1-byte immediate from the resulting encoding. Note that this transformation is not applied by gcc13 (according to my observations), so would - as of now - even improve compiler generated code.
2024-06-19x86: Remove the secondary encoding for ctest.Cui, Lili1-1/+0
There are two encodings for each opcode F6/F7 in ctest, but the second one is never used, so remove it to reduce the size of opcode_tbl.h. opcodes/ChangeLog: * i386-opc.tbl: Removed the secondary insn template for ctest. * i386-tbl.h: Regenerated.
2024-06-18Support APX CCMP and CTESTCui, Lili1-0/+19
CCMP and CTEST are two new sets of instructions for conditional CMP and TEST, SCC and OSZC flags are given as suffixes of CCMP or CTEST in the instruction mnemonic, e.g.: ccmp<cc> { dfv=sf , cf , of } %eax, %ecx also add {evex} cmp/test %eax, %ecx as an alias for ccmpt. For the encoder part, add function check_Scc_OszcOperation to parse '{ dfv=of , sf, sf, cf}', store scc in the lower 4 bits of base_opcode, and adjust base_opcode to its normal meaning in install_template. For the decoder part, add 'SC' and 'DF' macros to add scc and oszc flags suffixes. gas/ChangeLog: * config/tc-i386.c (OSZC_CF): New. (OSZC_ZF): Ditto. (OSZC_SF): Ditto. (OSZC_OF): Ditto. (set_oszc_flags): Set oszc flags and report error for using the same oszc flags twice. (check_Scc_OszcOperations): Handle SCC OSZC flags. (install_template): Add scc and oszc_flags. (build_apx_evex_prefix): Encode SCC and oszc flags bits. (parse_insn): Handle check_Scc_OszcOperations. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add ivalid test case. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add test for ccmp and ctest. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d: New test. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.d: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add ccmp and ctest. * i386-dis-evex.h: Ditto. * i386-dis.c (struct instr_info): add scc. (struct dis386): Add new micro 'NE','SC' and'DF'. (get_valid_dis386): Get scc value and move MAP4 invalid check to print_insn. (putop): Handle %NE, %SC and %DF. * i386-opc.h (SCC): New. * i386-opc.tbl: Add ccmp/ctest and evex format for cmp/test. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto.
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich1-2/+5
Extremely rarely used attributes are inefficient when represented by a separate attribute. Convert it to an operand constraint, as already suggested during review. The collision with RegKludge is pretty simple to resolve.
2024-06-10x86/APX: support extended SETcc formJan Beulich1-1/+4
As indicated during review, spelling/readability-wise setz %eax is easier than setzuz %al _and_ properly specifies the full register that's being modified. Permit that form to be used, even if the spec writers are unwilling to formally mention it. While there also correct the non-ZU EVEX form: That ought to also permit memory operands.
2024-06-10x86/APX: add missing CPU requirement to imm+rm forms of <alu2> insnsJan Beulich1-1/+1
This was overlooked when the form was added by dd74a603376e ("Support APX NF").
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich1-87/+87
Except for very few insns mnemonic suffixes aren't permitted in Intel syntax. Warn about such for now, indicating that they will be outright refused down the road. While fiddling with testcases to address fallout, drop a few things which should never have been tested as valid Intel syntax. Also add a previously missing line to simd-suffix.d.
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich1-8/+8
Properly reject inappropriate suffixes (No_lSuf / No_qSuf mistakenly omitted by cf665fee1d6c ["x86: re-work AVX512 embedded rounding / SAE"]), to avoid emitting bad or arbitrarily guessed instructions. Interestingly check_{long,qword}_suffix() don't help here, which perhaps is another indication that the way they work right now isn't quite appropriate. Sadly correcting just the templates breaks operand ambiguity detection, since so far that worked from a single template permitting more than one suffix. Here we have ambiguity though which can now be noticed only when taking all (matching) templates together. Therefore we need to determine further matching templates (see code comments for constraints), to then accumulate permitted suffixes across all of them.
2024-05-22Support APX zero-upperCui, Lili1-0/+6
This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili1-59/+61
gas/ChangeLog: * config/tc-i386.c (build_modrm_byte): Dropped the use of extension_opcode to encode the vvvv register. * testsuite/gas/i386/x86-64-sse2avx.d: Added new testcases. * testsuite/gas/i386/x86-64-sse2avx.s: Diito. opcodes/ChangeLog: * i386-opc.tbl: Added DstVVVV to some extension_opcode instructions. * i386-tbl.h: Regenerated.
2024-05-06x86: Drop SwapSourcesCui, Lili1-30/+30
gas/ChangeLog: * config/tc-i386.c (build_modrm_byte): Dropped the use of SWAP_SOURCES to encode the vvvv register. opcodes/ChangeLog: * i386-opc.h (SWAP_SOURCES): Dropped. (NO_DEFAULT_MASK): Adjusted the value. (ADDR_PREFIX_OP_REG): Ditto. (DISTINCT_DEST): Ditto. (IMPLICIT_STACK_OP): Ditto. (VexVVVV_SRC2): New. * i386-opc.tbl: Dropped SwapSources and replaced its VexVVVV with Src1VVVV. * i386-tbl.h: Regenerated.
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili1-565/+566
Use vexvvvv as the switch state, and replace VexVVVV with Src1VVVV. Src1VVVV means using VEX.vvvv encodes the first source register operand. The old logic did not check vexvvvv first, which made the logic here very complicated. gas/ChangeLog: * config/tc-i386.c (optimize_encoding): Replaced 1 with Src1VVVV. (build_modrm_byte): Used vexvvvv to encode the vvvv register. (s_insn): Replaced 1 with Src1VVVV. opcodes/ChangeLog: * i386-opc.h (VexVVVV_DST): Adjusted the value. (Src1VVVV): New. * i386-opc.tbl: Replaced part VexVVVV with Src1VVVV. * i386-tbl.h: Regenerated.
2024-05-03x86: tidy <sse*> templatesJan Beulich1-20/+20
Some of them no longer need a separate vvvv attribute, thus allowing them to be simplified. For <aes> the situation is slightly different: None of the remaining uses make use of vvvv anymore.
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich1-5/+6
Since {vex}/{vex3} are respected on legacy mnemonics when -msse2avx is in use, {evex} should be respected, too. So far this is the case only for insns where eGPR-s can come into play. Extend coverage to insns with only %xmm register and possibly immediate operands.
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich1-201/+303
Legacy encoded SIMD insns are converted to AVX ones in that mode. When eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where available; there are quite a few which can't be converted). Note that LDDQU is represented as VMOVDQU32 (and the prior use of the sse3 template there needs dropping, to get the order right). Note further that in a few cases, due to the use of templates, AVX512VL is used when AVX512F would suffice. Since AVX10 is the main reference, this shouldn't be too much of a problem.
2024-04-17Add W table for USER_MSR under MAP4.Hu, Lin11-1/+1
opcodes/ChangeLog: * i386-dis-evex-mod.h: Modify MOD_EVEX_MAP4_F8_P1, MOD_EVEX_MAP4_F8_P3. * i386-dis-evex-w.h (EVEX_W_MAP4_F8_P1_M_1): New. (EVEX_W_MAP4_F8_P3_M_1): Ditto. * i386-dis.c (vex_w_table): Add EVEX_W_MAP4_F8_P1_M_1, EVEX_W_MAP4_F8_P3_M_1. * i386-opc.tbl: Remove redundant '|'.
2024-04-07Support APX NFCui, Lili1-2/+21
For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-06Revert "x86: Restore APX shift-double instructions with omitted shift count"H.J. Lu1-1/+0
This reverts commit c2d698fe03a6092d58a07de96068b87836daced0. GCC 14 has been changed to use explicit shift count in shift-double instructions by the commit: 06a7e7514af x86: Use explicit shift count in double-precision shifts gas/ PR gas/31606 * testsuite/gas/i386/x86-64-apx-ndd-wig.d: Updated. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.s: Remove tests for APX shift-double instructions with omitted shift count. opcodes/ PR gas/31606 * i386-opc.tbl: Remove APX shift-double instructions with omitted shift count. * i386-tbl.h: Regenerated.
2024-04-04x86: Restore APX shift-double instructions with omitted shift countH.J. Lu1-0/+1
Restore APX shift-double instructions with omitted shift count since they are generated by GCC as shown in: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114590 gas/ PR gas/31606 * testsuite/gas/i386/x86-64-apx-ndd-wig.d: Updated. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.s: Add tests for APX shift-double instructions with omitted shift count. opcodes/ PR gas/31606 * i386-opc.tbl: Restore APX shift-double instructions with omitted shift count. * i386-tbl.h: Regenerated.
2024-04-03x86: add missing No_qSuf to non-64-bit PTWRITEJan Beulich1-1/+1
While largely benign, it still should have been put there when the original single template was split (commit a04973848dc5).
2024-04-03x86: drop stray Size64 from WRSSQJan Beulich1-2/+2
Like for WRUSSQ it's not needed here. The legacy insn had gained it in the course of zapping Rex64, but that attribute wasn't needed here either. The APX insn then simply gained it by copy-and-paste, I suppose.
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-18/+0
APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gas/ChangeLog: * NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX * MAP4. * config/tc-i386.c (process_operands): Removed special handling of * KEYLOCKER and SHA. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER * and SHA instructions. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions. * i386-dis-evex.h: Ditto. * i386-opc.tbl: Ditto. * i386-dis.c (print_vector_reg): Removed special handling of KEYLOCKER * and SHA.
2024-03-28x86: templatize RAO-INT insnsJan Beulich1-8/+4
It's only four of them, but still better to reduce redundancy.
2024-03-28x86: templatize ADX insnsJan Beulich1-6/+5
It's only two of them, but still better to reduce redundancy.
2024-03-28x86: templatize shift-double insnsJan Beulich1-13/+9
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with the shift-double ones. While there also drop the APX form with ShiftCount omitted. Other shift and rotate insns were deliberately left without this form as well. Note that there's also no testsuite adjustment needed for this, indicating that the form wasn't tested either.
2024-03-28x86: templatize shift/rotate insnsJan Beulich1-71/+22
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with the "ordinary" shift and rotate ones. While there also drop the APX form of RCL/RCR with Imm1 omitted. Other shift insns as well as ROR/ROL were deliberately left without this form as well. Note that there's also no testsuite adjustment needed for this, indicating that the form wasn't tested either. Furthermore since RCL/RCR already had non-NDD APX forms, those end up being added for the other 6 mnemonics, too.
2024-03-28x86: templatize binary ALU insnsJan Beulich1-59/+23
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with a the more complex binary (two source) cases. Note how this adds a missing CheckOperandSize to one of the APX sub forms. Furthermore since SBB already had a non-NDD APX form, one ends up being added for the other 6 mnemonics, too.
2024-03-28x86: templatize unary ALU insnsJan Beulich1-10/+16
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with a few simple unary (single source) cases.
2024-03-28x86: templatize INC/DECJan Beulich1-8/+8
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Start with the simplest case, accompanied by a necessary adjustment to i386-gen (such that template uses can also be at the start of a line). While there also drop a bogus (meaningless / unreachable) "break" as well as a unused variable (which I'm surprised compilers didn't warn about).
2024-03-01x86/APX: optimize certain XOR and SUB formsJan Beulich1-2/+2
While most logic in optimize_encoding() is already covering APX by way of the earlier NDD->REX2 conversion, there's a remaining set of cases which wants handling separately.
2024-02-23x86/APX: INV{EPT,PCID,VPID} are WIGJan Beulich1-3/+3
While various other entries in version 003 of the spec aren't quite as explicit (due to simply leaving the respective field blank), all three have a clear IGNORED there. IOW they ought to be emitted with EVEX.W=0 by default (and respect -mevexwig=).
2024-02-16x86/APX: drop stray IgnoreSizeJan Beulich1-11/+11
While necessary on the legacy encodings, the EVEX ones don't need it. Even more so when they're available for 64-bit mode only, when the legacy encodings have the attribute only for correctly handling things in 16-bit mode.
2024-02-16x86: don't use VexWIG in SSE2AVX templatesJan Beulich1-4/+4
Several years ago it was decided that SSE2AVX templates should not be sensitive to -mvexwig= (upon my suggestion to consistently make all sensitive as long as they don't require a specific setting of VEX.W). Adjust the four that still are, switching to use of Vex128 at the same time.
2024-02-16x86: drop redundant XmmwordJan Beulich1-8/+8
While e20298da05f2 ("Remove redundant Byte, Word, Dword and Qword from insn templates") did so for Byte/Word/Dword/Qword, the same kind of redundancy was left in place for a few 128-bit SIMD operands.
2024-02-09x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressedJan Beulich1-4/+16
Interestingly unlike VROUND{P,S}{S,D} and VPERM{F,I}128 they weren't even present in the x86-64-apx-egpr-inval testcase, hence why I overlooked that these can actually be encoded, (again) using suitable AVX512 counterparts. While there also "modernize" the adjacent AVX/AVX2 entries.
2024-02-09x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL}Jan Beulich1-2/+2
In eea4357967b6 ("x86/APX: VROUND{P,S}{S,D} can generally be encoded") I failed to add the AVX512* ISA dependency of the two new entries.
2024-01-26x86/APX: optimize MOVBEJan Beulich1-2/+4
With identical source and destination it can be covered by the NDD-to- legacy conversion logic as well, even if in this case the original insn doesn't use an NDD encoding. The size savings are even better here, for the replacement (BSWAP) not having a ModR/M byte.
2024-01-19x86/APX: VROUND{P,S}{S,D} can generally be encodedJan Beulich1-0/+4
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As long as the immediate has the top 4 bits clear, they are equivalent to the earlier VEX-encoded insns, and hence can be used to permit use of eGPR-s in the memory operand. Since this is the normal way of using these insns, also alter the resulting diagnostic to complain about the immediate, not the eGPR use.
2024-01-19x86: drop redundant EVex128 from PUSH2/POP2Jan Beulich1-4/+4
EVexMap4 already covers that.
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich1-2/+4
This was missed in 6177c84d5edc ("Support APX GPR32 with extend evex prefix").
2024-01-15opcodes: x86: new marker for insns that implicitly update stack pointerIndu Bhagat1-52/+53
Some x86 instructions affect the stack pointer implicitly. Add a new operand constraint to reflect this. This will be useful for SCFI implmentation to ensure its correctness. Mark all push, pop, call, ret, enter, leave, INT, iret instructions. opcodes/ * i386-gen.c: Update opcode_modifiers. * i386-opc.h: Add a new constraint. * i386-opc.tbl: Update the affected instructions. * i386-tbl.h: Regenerated.
2024-01-15opcodes: gas: x86: define and use Rex2 as attribute not constraintIndu Bhagat1-1/+0
Rex2 is currently an operand constraint. For the upcoming SCFI implementation in GAS, we need to identify operations which implicitly update the stack pointer. An operand constraint enumerator for implicit stack op seems more appropriate than an attribute. However, two opcodes currently necessitate both Rex2 and an implicit stack op marker; this prompts revisiting the current representations a bit. Make Rex2 a standalone attribute, so that later a new operand constraint may be added for IMPLICIT_STACK_OP. ChangeLog: * gas/config/tc-i386.c (is_apx_rex2_encoding): Update the check. * opcodes/i386-gen.c: Add a new BITFIELD for Rex2. * opcodes/i386-opc.h (REX2_REQUIRED): Remove. * opcodes/i386-opc.tbl: Remove Rex2 operand constraint. * opcodes/i386-tbl.h: Regenerated.
generated by cgit v1.1 at 2024-07-10 13:28:42 +0000