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| author | Jan Beulich <jbeulich@suse.com> | 2024-06-28 08:19:32 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-06-28 08:19:32 +0200 |
| commit | c7eae03eab750f93b6460e883f25b71d46dd1c47 (patch) | |
| tree | 66525e230d31b82444d94c01410f45bec81e6a2a /opcodes/i386-opc.tbl | |
| parent | 0868b8999bbca960781e7d8bbbc363536193a694 (diff) | |
| download | fsf-binutils-gdb-c7eae03eab750f93b6460e883f25b71d46dd1c47.zip fsf-binutils-gdb-c7eae03eab750f93b6460e883f25b71d46dd1c47.tar.gz fsf-binutils-gdb-c7eae03eab750f93b6460e883f25b71d46dd1c47.tar.bz2 | |
x86/APX: optimize {nf}-form rotate-by-width-less-1
Unlike for the legacy forms, where there's a difference in the resulting
EFLAGS.CF, for the NF variants the immediate can be got rid of in that
case by switching to a 1-bit rotate in the opposite direction.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 2715c5e..bf4ecdb 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -446,22 +446,22 @@ imulzu, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF/*|ZU*/, { Imm16 <div> -<sr:opc:imm8:opt1:nf, + - rol:0:Imm8|Imm8S::NF, + - ror:1:Imm8|Imm8S::NF, + - rcl:2:Imm8::, + - rcr:3:Imm8::, + - sal:4:Imm8:Optimize:NF, + - shl:4:Imm8:Optimize:NF, + - shr:5:Imm8::NF, + - sar:7:Imm8::NF> +<sr:opc:imm8:opt1:opti:nf, + + rol:0:Imm8|Imm8S::Optimize:NF, + + ror:1:Imm8|Imm8S::Optimize:NF, + + rcl:2:Imm8:::, + + rcr:3:Imm8:::, + + sal:4:Imm8:Optimize::NF, + + shl:4:Imm8:Optimize::NF, + + shr:5:Imm8:::NF, + + sar:7:Imm8:::NF> <sr>, 0xd0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:opt1>|<sr:nf>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } <sr>, 0xd0/<sr:opc>, 0, W|Modrm|No_sSuf|<sr:opt1>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } <sr>, 0xd0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:opt1>|<sr:nf>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:opti>|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } <sr>, 0xc0/<sr:opc>, i186, W|Modrm|No_sSuf, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } +<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:opti>|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } <sr>, 0xd2/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:nf>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } <sr>, 0xd2/<sr:opc>, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } <sr>, 0xd2/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:nf>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |