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| author | Jan Beulich <jbeulich@suse.com> | 2024-06-10 09:05:23 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-06-10 09:05:23 +0200 |
| commit | d967140f8ca04a3fbe607382d615af35f9df9453 (patch) | |
| tree | b9d71566b39386b0eaed0864db5dbcb385b2c19b /opcodes/i386-opc.tbl | |
| parent | db335d7e0ad5d7422299e91e883bc87236a67f2f (diff) | |
| download | fsf-binutils-gdb-d967140f8ca04a3fbe607382d615af35f9df9453.zip fsf-binutils-gdb-d967140f8ca04a3fbe607382d615af35f9df9453.tar.gz fsf-binutils-gdb-d967140f8ca04a3fbe607382d615af35f9df9453.tar.bz2 | |
x86/APX: add missing CPU requirement to imm+rm forms of <alu2> insns
This was overlooked when the form was added by dd74a603376e ("Support
APX NF").
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 144a7f4..ac14bee 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -324,7 +324,7 @@ sti, 0xfb, 0, NoSuf, {} <alu2>, <alu2:opc> << 3, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|<alu2:nf>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } <alu2>, 0x83/<alu2:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } <alu2>, 0x83/<alu2:opc>, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|<alu2:opti>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } -<alu2>, 0x83/<alu2:opc>, 0, Modrm|No_bSuf|No_sSuf|EVexMap4|<alu2:nf>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } +<alu2>, 0x83/<alu2:opc>, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|<alu2:nf>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } <alu2>, 0x04 | (<alu2:opc> << 3), 0, W|No_sSuf|<alu2:opti>, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } <alu2>, 0x80/<alu2:opc>, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } <alu2>, 0x80/<alu2:opc>, 0, W|Modrm|No_sSuf|HLEPrefixLock|<alu2:opti>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } |