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| author | Jan Beulich <jbeulich@suse.com> | 2024-02-09 08:38:52 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-02-09 08:38:52 +0100 |
| commit | 5a635f1f59ad08e572e36419f1145433fd670214 (patch) | |
| tree | 64073599f5c82f8a451d822539d5ca08fba0375f /opcodes/i386-opc.tbl | |
| parent | 066673f6d5ef258b9534f6baaa3d52fa35905b00 (diff) | |
| download | fsf-binutils-gdb-5a635f1f59ad08e572e36419f1145433fd670214.zip fsf-binutils-gdb-5a635f1f59ad08e572e36419f1145433fd670214.tar.gz fsf-binutils-gdb-5a635f1f59ad08e572e36419f1145433fd670214.tar.bz2 | |
x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL}
In eea4357967b6 ("x86/APX: VROUND{P,S}{S,D} can generally be encoded") I
failed to add the AVX512* ISA dependency of the two new entries.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 55c704b..e79e5ba 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1794,8 +1794,8 @@ vroundp<sd>, 0x6608 | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexWIG|CheckOperandSize vrounds<sd>, 0x660a | <sd:opc>, AVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } // These are really clones of VRNDSCALE{P,S}{S,D}, with broadcast, masking, SAE, // 512-bit operand size, and register sources dropped. -vroundp<sd>, 0x6608 | <sd:opc>, APX_F, Modrm|Space0F3A|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vrounds<sd>, 0x660a | <sd:opc>, APX_F, Modrm|EVexLIG|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } +vroundp<sd>, 0x6608 | <sd:opc>, APX_F&AVX512VL, Modrm|Space0F3A|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vrounds<sd>, 0x660a | <sd:opc>, APX_F&AVX512F, Modrm|EVexLIG|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } vrsqrtps, 0x52, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vrsqrtss, 0xf352, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vshufp<sd>, 0x<sd:ppfx>c6, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |