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| author | H.J. Lu <hjl.tools@gmail.com> | 2024-04-04 13:12:12 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2024-04-04 13:16:20 -0700 |
| commit | c2d698fe03a6092d58a07de96068b87836daced0 (patch) | |
| tree | 24a5ff2e1bc799771f259dd02e90b79f63e35a44 /opcodes/i386-opc.tbl | |
| parent | 16810e455feb26ef826a3ed876d6d7e6d24818b0 (diff) | |
| download | fsf-binutils-gdb-c2d698fe03a6092d58a07de96068b87836daced0.zip fsf-binutils-gdb-c2d698fe03a6092d58a07de96068b87836daced0.tar.gz fsf-binutils-gdb-c2d698fe03a6092d58a07de96068b87836daced0.tar.bz2 | |
x86: Restore APX shift-double instructions with omitted shift count
Restore APX shift-double instructions with omitted shift count since
they are generated by GCC as shown in:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114590
gas/
PR gas/31606
* testsuite/gas/i386/x86-64-apx-ndd-wig.d: Updated.
* testsuite/gas/i386/x86-64-apx-ndd.d: Likewise.
* testsuite/gas/i386/x86-64-apx-ndd.s: Add tests for APX
shift-double instructions with omitted shift count.
opcodes/
PR gas/31606
* i386-opc.tbl: Restore APX shift-double instructions with
omitted shift count.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 5d0c81b..fc689d4 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -434,6 +434,7 @@ imul, 0x69, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|R sh<shd>d, 0x24 | <shd:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } sh<shd>d, 0x0fa4 | <shd:opc>, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } +sh<shd>d, 0xa5 | <shd:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } sh<shd>d, 0xa5 | <shd:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } sh<shd>d, 0x0fa5 | <shd:opc>, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } sh<shd>d, 0x0fa5 | <shd:opc>, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } |