Support APX CCMP and CTEST

CCMP and CTEST are two new sets of instructions for conditional CMP
and TEST, SCC and OSZC flags are given as suffixes of CCMP or CTEST
in the instruction mnemonic, e.g.:

ccmp<cc> { dfv=sf , cf , of } %eax, %ecx

also add

{evex} cmp/test %eax, %ecx

as an alias for ccmpt.

For the encoder part, add function check_Scc_OszcOperation to parse
'{ dfv=of , sf, sf, cf}', store scc in the lower 4 bits of base_opcode,
and adjust base_opcode to its normal meaning in install_template.

For the decoder part, add 'SC' and 'DF' macros to add scc and oszc flags
suffixes.

gas/ChangeLog:

        * config/tc-i386.c (OSZC_CF): New.
        (OSZC_ZF): Ditto.
        (OSZC_SF): Ditto.
        (OSZC_OF): Ditto.
        (set_oszc_flags): Set oszc flags and report error for using the same oszc flags twice.
        (check_Scc_OszcOperations): Handle SCC OSZC flags.
        (install_template): Add scc and oszc_flags.
        (build_apx_evex_prefix): Encode SCC and oszc flags bits.
        (parse_insn): Handle check_Scc_OszcOperations.
        * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add ivalid test case.
        * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
        * testsuite/gas/i386/x86-64.exp: Add test for ccmp and ctest.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d: New test.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l: Ditto.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s: Ditto.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest.d: Ditto.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest.s: Ditto.

opcodes/ChangeLog:

        * i386-dis-evex-reg.h: Add ccmp and ctest.
        * i386-dis-evex.h: Ditto.
        * i386-dis.c (struct instr_info): add scc.
        (struct dis386): Add new micro 'NE','SC' and'DF'.
        (get_valid_dis386): Get scc value and move MAP4 invalid check to print_insn.
        (putop): Handle %NE, %SC and %DF.
        * i386-opc.h (SCC): New.
        * i386-opc.tbl: Add ccmp/ctest and evex format for cmp/test.
        * i386-mnem.h: Regenerated.
        * i386-tbl.h: Ditto.

1 files changed, 19 insertions, 0 deletions

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index c910680..e365f06 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -86,6 +86,7 @@
 #define Ugh               OperandConstraint=UGH
 #define ImplicitStackOp   OperandConstraint=IMPLICIT_STACK_OP
 #define ZU                OperandConstraint=ZERO_UPPER
+#define Scc               OperandConstraint=SCC
 
 #define ATTSyntax         Dialect=ATT_SYNTAX
 #define ATTMnemonic       Dialect=ATT_MNEMONIC
@@ -341,10 +342,28 @@ cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8
 cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 cmp, 0x3c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 cmp, 0x80/7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+cmp, 0x380a, APX_F, D|W|CheckOperandSize|EVexMap4|Scc|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+cmp, 0x830a/7, APX_F, Modrm|EVexMap4|Scc|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+cmp, 0x800a/7, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+
+<scc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, +
+         s:8, ns:9, t:a, f:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
+
+ccmp<scc>, 0x380<scc:opc>, APX_F, D|W|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ccmp<scc>, 0x830<scc:opc>/7, APX_F, Modrm|EVexMap4|Scc|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ccmp<scc>, 0x800<scc:opc>/7, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+test, 0x840a, 0, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+test, 0xf60a/0, 0, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+
+ctest<scc>, 0x840<scc:opc>, APX_F, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ctest<scc>, 0xf60<scc:opc>/0, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ctest<scc>, 0xf60<scc:opc>/1, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+
+<scc>
 
 <incdec:opc, inc:0, dec:1>