- May 21, 2024
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Timm Bäder authored
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Lukacma authored
This patch extends https://reviews.llvm.org/D68611 and emits lifetime markers for temporary allocas of non-aggregate types as well.
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Timm Bäder authored
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Florian Hahn authored
Use getStartAndEndForAccess to compute the start and end of both src and sink (factored out to helper in bce3680f). If they do not overlap (i.e. SrcEnd <= SinkStart || SinkEnd <= SrcStart), there is no dependence, regardless of stride. PR: https://github.com/llvm/llvm-project/pull/92307
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Kiran Chandramohan authored
Fix an issue where the lastprivate variable type is different from the type used for the index of the loop. Fixes #79780
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Timm Bäder authored
Both types need to boil down to a vector type with the same length and their element types need to match, but we still can't compare them with == since they might be sugared, etc.
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Pavel Labath authored
Also make it a int32_t to match the surrounding code.
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martinboehme authored
This component can be useful when creating implementations of `Solver`, as some SAT solvers require the input to be in 3-CNF. As part of making `CNFFormula` externally accessible, I have moved some member variables out of it that aren't really part of the representation of a 3-CNF formula and thus live better elsewhere: * `WatchedHead` and `NextWatched` have been moved to `WatchedLiteralsSolverImpl`, as they're part of the specific algorithm used by that SAT solver. * `Atomics` has become an output parameter of `buildCNF()` because it has to do with the relationship between a `CNFFormula` and the set of `Formula`s it is derived from rather than being an integral part of the representation of a 3-CNF formula. I have also made all member variables private and added appropriate accessors.
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Florian Hahn authored
This fixes some cases where predicated BBs where missed previously, leading to under-estimating the cost of those blocks.
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Kiran Chandramohan authored
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Matt Arsenault authored
Fix copy paste error using align 4 double atomics. Test the meaningful correctly aligned cases, the unaligned case emits broken libcalls.
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Matt Arsenault authored
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Pavel Labath authored
…unction (#91321)" This reapplies fd1bd53b, which was reverted due to a test failure on aarch64/windows. The failure was caused by a combination of several factors: - clang targeting aarch64-windows (unlike msvc, and unlike clang targeting other aarch64 platforms) defaults to -fomit-frame-pointers - lldb's code for looking up register values for `<same>` unwind rules is recursive - the test binary creates a very long chain of fp-less function frames (it manages to fit about 22k frames before it blows its stack) Together, these things have caused lldb to recreate the same deep recursion when unwinding through this, and blow its own stack as well. Since lldb frames are larger, about 4k frames like this was sufficient to trigger the stack overflow. This version of the patch works around this problem by increasing the frame size of the test binary, thereby causing it to blow its stack sooner. This doesn't fix the issue -- the same problem can occur with a real binary -- but it's not very likely, as it requires an infinite recursion in a simple (so it doesn't use the frame pointer) function with a very small frame (so you can fit a lot of them on the stack). A more principled fix would be to make lldb's lookup code non-recursive, but I believe that's out of scope for this patch. The original patch description follows: A leaf function may not store the link register to stack, but we it can still end up being a non-zero frame if it gets interrupted by a signal. Currently, we were unable to unwind past this function because we could not read the link register value. To make this work, this patch: - changes the function-entry unwind plan to include the `fp|lr = <same>` rules. This in turn necessitated an adjustment in the generic instruction emulation logic to ensure that `lr=[sp-X]` can override the `<same>` rule. - allows the `<same>` rule for pc and lr in all `m_all_registers_available` frames (and not just frame zero). The test verifies that we can unwind in a situation like this, and that the backtrace matches the one we computed before getting a signal.
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Nikita Popov authored
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Pavel Labath authored
VSCode will automatically ask for the children (in structured form) so there's no point in sending the textual representation. This can make displaying hover popups for complex variables with complicated data formatters much faster. See discussion on #77026 for context.
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Owen Pan authored
Fixes #92300.
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Nikita Popov authored
To minimize future diffs.
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Christopher Di Bella authored
`remove_cv_t` and `remove_all_extents_t` are taken care of by the built-in trait, so we don't need to use them directly. --------- Co-authored-by:Louis Dionne <ldionne.2@gmail.com>
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Zibi authored
Follow up to llvm#92261.
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Nikita Popov authored
This was one of the last leftovers still using a Create-style instead of Fold-style API. Convert FoldICmp into FoldCmp so it can handle both icmp and fcmp.
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hev authored
This PR enables interleaved vectorization for LoongArch, with a default interleaving factor of `2`.
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Nikita Popov authored
Use ConstantFoldCompareInstOperands() instead.
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Vlad Serebrennikov authored
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Ramkumar Ramachandra authored
Lift out the long lambdas into static functions, use C++ destructing syntax, and fix other minor things to improve the readability of the function.
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Cullen Rhodes authored
vector.transpose ops whose inputs come from vector.transfer_read can be eliminated by folding the transpose into the xfer op to enable in-flight transposition when converting xfer read to arm_sme.tile_load.
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Ramkumar Ramachandra authored
21419071 (InstSimplify: increase shufflevector test coverage) was recently merged as a pre-commit test for some work that was misguided. It turns out that InstSimplify can never work on those tests, but the tests are useful nevertheless; move them to VectorCombine to support the development of VectorCombine::foldShuffleToIdentity.
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Ramkumar Ramachandra authored
foldIdentityShuffles requires two sets of canceling shuffles. If there are any intervening instructions, they are feeding in the result of the first set of shuffles. To eliminate the two sets of shuffles, you'd have to rewrite the head of the intervening instructions to feed in the operand of the first set of shuffles. Since modifying the IR in any way is disallowed by an analysis, strip this bad TODO.
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Yuxuan Chen authored
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Piyou Chen authored
This patch try to get rid of vsetvl implict vl/vtype def-use chain and improve the register allocation quality by moving the vsetvl insertion pass after RVV register allocation It will gain the benefit for the following optimization from 1. unblock scheduler's constraints by removing vl/vtype def-use chain 2. Support RVV re-materialization 3. Support partial spill This patch add a new option `-riscv-vsetvl-after-rvv-regalloc=<1|0>` to control this feature and default set as disable.
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Nikita Popov authored
The code was essentially already ready to handle multiple indices -- we only need to adjust the non-negative index check to check all indices, instead of only the first one.
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zhongyunde 00443407 authored
We remove the combine for fmuladd with fast flag on PR90434, and add these tests with reduced flags to show they have identity results.
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zhongyunde 00443407 authored
We should treat fmuladd like an fma intrinsic, and any regressions need to be addressed by dealing with fma/fmuladd in other contexts.
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Craig Topper authored
I think the behaviors are the same if this describes their behavior. AVGFLOORS sign extends the inputs by 1 bit, adds them, then does an arithmetic shift right by 1 before truncating to the original bit width. This is vaadd with rdn rounding mode. AVGCEILS sign extends the inputs by 1 bit, adds them, then does an arithmetic shift right by 1. If the bit shifted out is 1, it adds 1 to the shifted value. Then truncates to the original bit width. This is vaadd with rnu rounding mode. I think this wasn't implemented previously because there was some confusion about what average means. Some may expect average to round towards zero, but there is no way to do that in RISC-V or with the SelectionDAG nodes. Related issue https://github.com/riscv/riscv-v-spec/issues/935
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henke9600 authored
Found this while trying to build a LLVM toolchain reproducibly from both Debian 12 and FreeBSD 14. With these changes they come out bit-by-bit identical. Previously there was a mix of stable and unstable sorts for slices, now only stable sorts are used.
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Luke Lau authored
We have two rules in needVSETVLI where we can relax the demanded fields for slides and splats when VL=1. However these aren't present in getDemanded which prevents us from coalescing some vsetvlis around slides and splats in the backwards pass. The reasoning as to why they weren't in getDemanded is that these require us to check the value of the AVL operand, which may be stale in the backwards pass: the actual VL or VTYPE value may differ from what was precisely requested in the pseudo's operands. Using the original operands should actually be fine though, as we only care about what was originally demanded by the instruction. The current value of VL or VTYPE shouldn't influence this. This addresses some of the regressions we are seeing in #70549 from splats and slides getting reordered.
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Matt Arsenault authored
This avoids depending on pre/post link runs. Depends #92595
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Kazu Hirata authored
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Adrian Kuegel authored
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Nikita Popov authored
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