- Sep 12, 2023
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Wenjing Liu authored
[why] build scaling param is overriding validation policy regarding small viewport support. Even if ODM + windowed MPO is not supported. The decision has to be made at the time of validation. When building scaling params, we might be building an initial dc state as an input to DML validation. The initial state is not supposed to be always valid and we rely on DML to modify the initial dc state and determine the final validation result. This check is pre judging validation result when building the initial dc state. This causes an issue where we are transitioning from desktop only ODM combine 2:1 to ODM bypass with 2 planes. In this case we are building an initial state with with ODM 2:1 combine + 2 planes. This is indeed not supported but DML is about to modify the state so it no longer uses ODM combine. Before it reaches DML, dc resource already fails validation because it checks that the initial state is not supported by our policy. This overrides the ODM decision to validate this state with ODM combine disabled. Therefore causes an unexpected validation failure when the secondary plane is added on one side of the screen. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Susanto authored
[Why] DML calculations differ with DCN3.1 spreadsheet values due to translations errors from the visual basic code [How] Add missing calculations that set the value for DSCDelay Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Tao Zhou authored
Print out row, column and bank value of UMC error address for UMC v12. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Hawking Zhang authored
So driver doesn't generate incorrect message until the new format is settled down for aqua_vanjaram Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Alex Deucher authored
Needed for HDP flush to work correctly. Reviewed-by:
Timmy Tsai <timmtsai@amd.com> Signed-off-by:
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Alex Deucher authored
This matches the behavior for soc15 and nv. Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Anthony Koo authored
- Add new params to dmub_feature_caps for checking replay support in FW Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Swapnil Patel authored
[Why] Currently the driver looks DCN registers to access if BL is on or not. This check is not valid if we are using AUX based brightness control. This causes driver to not send out "backlight off" command during power off sequence as it already thinks it is off. [How] Only check DCN registers if we aren't using AUX based brightness control. Reviewed-by:
Swapnil Patel <swapnil.patel@amd.com> Tested-by:
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Dan Carpenter authored
This loop will exit with "retry" set to -1 if it fails but the code checks for if "retry" is zero. Fix this by changing post-op to a pre-op. --retry vs retry--. Fixes: e01eeffc ("drm/amd/pm: avoid driver getting empty metrics table for the first time") Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
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Bhawanpreet Lakha authored
Dirty rect can be used with replay, so enable them to allow for more powersaving. Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Acked-by:
Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] Set a default return value of -ENOTSUPP to indicate that the hardware does not support querying ODM Combine mode. Reviewed-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Hamza Mahfooz authored
This reverts commit 70e64c4d . Since, we now have an actual fix for this issue, we can get rid of this workaround as it can cause pin failures if enough VRAM isn't carved out by the BIOS. Cc: stable@vger.kernel.org # 6.1+ Acked-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Yifan Zhang authored
Dropping bit 31:4 of page table base is wrong, it makes page table base points to wrong address if phys addr is beyond 64GB; dropping page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup will do that. Also, while we are at it, cleanup the assignments using upper_32_bits()/lower_32_bits() and AMDGPU_GPU_PAGE_SHIFT. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 Fixes: 81d0bcf9 ("drm/amdgpu: make display pinning more flexible (v2)") Acked-by:
Yifan Zhang <yifan1.zhang@amd.com> Co-developed-by:
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Alvin Lee authored
[Description] - When disabling a phantom pipe, we first enable the phantom OTG so the double buffer update can successfully take place - However, want to avoid locking the phantom otherwise setting DPG_EN=1 for the phantom pipe is blocked (without this we could hit underflow due to phantom HUBP being blanked by default) Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Alvin Lee authored
[Description] Before enabling the phantom OTG for an update we must enable DPG to avoid underflow. Reviewed-by:
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Mukul Joshi authored
The CU mask passed from user-space will change based on different spatial partitioning mode. As a result, update CU masking code for GFX9.4.3 to work for all partitioning modes. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Mukul Joshi authored
Update cache info reporting in sysfs to report the correct number of CUs and associated cache information based on different spatial partitioning modes. Signed-off-by:
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Tao Zhou authored
Get UMC phyical channel index according to node id, umc instance and channel instance. Signed-off-by:
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Yang Wang authored
v1: enable smu_v13_0_6 mca debug mode when UMC RAS feature is enabled. v2: use amdgpu_ras_is_supported() helper function instead bitmask check. Signed-off-by:
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Yang Wang authored
update smu firmware header to support smu mca debug feature. Signed-off-by:
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Tao Zhou authored
Convert MCA error address to physical address and find out all pages in one physical row. Signed-off-by:
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Lijo Lazar authored
When reset method is not passed in reset context, look for the handler for default reset method. On Aldebaran, default reset method for SOCs connected to CPU over XGMI is MODE2. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Tested-by:
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Mukul Joshi authored
Currently, we store CU info only for a single XCC assuming that it is the same for all XCCs. However, that may not be true. As a result, store CU info for all XCCs. This info is later used for CU masking. Signed-off-by:
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Ma Jun authored
[1] Remove the irq flags setting code since pci_alloc_irq_vectors() handles these flags. [2] Free the msi vectors in case of error. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Acked-by:
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Lang Yu authored
Fixes: 5d5eac7e ("drm/amdgpu: add selftest framework for UMSCH") Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
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Mukul Joshi authored
This patch fixes the following unaligned 64-bit doorbell warning seen when submitting packets on HIQ on GFX v9.4.3 by making the HIQ doorbell 64-bit aligned. The warning is seen when GPU is loaded in any mode other than SPX mode. [ +0.000301] ------------[ cut here ]------------ [ +0.000003] Unaligned 64-bit doorbell [ +0.000030] WARNING: /amdkfd/kfd_doorbell.c:339 write_kernel_doorbell64+0x72/0x80 [ +0.000003] RIP: 0010:write_kernel_doorbell64+0x72/0x80 [ +0.000004] RSP: 0018:ffffc90004287730 EFLAGS: 00010246 [ +0.000005] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000 [ +0.000003] RDX: 0000000000000001 RSI: ffffffff82837c71 RDI: 00000000ffffffff [ +0.000003] RBP: ffffc90004287748 R08: 0000000000000003 R09: 0000000000000001 [ +0.000002] R10: 000000000000001a R11: ffff88a034008198 R12: ffffc900013bd004 [ +0.000003] R13: 0000000000000008 R14: ffffc900042877b0 R15: 000000000000007f [ +0.000003] FS: 00007fa8c7b62000(0000) GS:ffff889f88400000(0000) knlGS:0000000000000000 [ +0.000004] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ +0.000003] CR2: 000056111c45aaf0 CR3: 00000001414f2002 CR4: 0000000000770ee0 [ +0.000003] PKRU: 55555554 [ +0.000002] Call Trace: [ +0.000004] <TASK> [ +0.000006] kq_submit_packet+0x45/0x50 [amdgpu] [ +0.000524] pm_send_set_resources+0x7f/0xc0 [amdgpu] [ +0.000500] set_sched_resources+0xe4/0x160 [amdgpu] [ +0.000503] start_cpsch+0x1c5/0x2a0 [amdgpu] [ +0.000497] kgd2kfd_device_init.cold+0x816/0xb42 [amdgpu] [ +0.000743] amdgpu_amdkfd_device_init+0x15f/0x1f0 [amdgpu] [ +0.000602] amdgpu_device_init.cold+0x1813/0x2176 [amdgpu] [ +0.000684] ? pci_bus_read_config_word+0x4a/0x80 [ +0.000012] ? do_pci_enable_device+0xdc/0x110 [ +0.000008] amdgpu_driver_load_kms+0x1a/0x110 [amdgpu] [ +0.000545] amdgpu_pci_probe+0x197/0x400 [amdgpu] Fixes: c3186665 ("drm/amdgpu: use doorbell mgr for kfd kernel doorbells") Signed-off-by:
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Mukul Joshi authored
This patch fixes the case where the code currently passes absolute register address and not the reg offset, which HWS expects, when sending the PM4 packet to set/update CWSR grace period. Additionally, cleanup the signature of build_grace_period_packet_info function as it no longer needs the inst parameter. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
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- Sep 07, 2023
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Yang Li authored
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn35/dcn35_fpu.c:260 dcn35_update_bw_bounding_box_fpu() warn: inconsistent indenting Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Candice Li authored
Add umc v12_0 ras error querying. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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Lijo Lazar authored
SMU v13.0.6 SOCs have 100MHz reference clock. Signed-off-by:
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Hawking Zhang authored
gfx_v9_4_3_ue|ce_reg_list is an array per gfx core instance correct the settings of se_num and reg_inst for some of gfx ras counters so all the available register instances can be polled for ras status. Signed-off-by:
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Lijo Lazar authored
Restrict the wait for boot loader steady state only to SMUv13.0.6. For older SOCs, ASIC init has a longer wait period and that takes care. Signed-off-by:
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Lijo Lazar authored
Show only firmware version attributes that have valid version. Hide others. Signed-off-by:
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Lang Yu authored
Use proper type. Fixes: 9d4346bd ("drm/amdgpu: add VPE 6.1.0 support") Signed-off-by:
Solomon Chiu <solomon.chiu@amd.com> Reviewed-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202309020608.FwP8QMht-lkp@intel.com Signed-off-by:
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Srinivasan Shanmugam authored
Use min_t to replace min, min_t is a bit fast because min use twice typeof. And using min_t is cleaner here since the min/max macros do a typecheck while min_t()/max_t() to an explicit type cast. Fixes the below checkpatch warning: WARNING: min() should probably be min_t() Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by:
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Candice Li authored
Add umc v12_0_0 ip headers. Signed-off-by:
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Candice Li authored
Only calculate pcie_index_hi for register address greater than 32bits. Signed-off-by:
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Candice Li authored
Add 64bits register access support on register whose address is greater than 32bits. Signed-off-by:
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Srinivasan Shanmugam authored
This warning is for the declaration of a static array, and it is recommended to declare it as type "static const char * const" instead of "static const char *". an array pointer declared as type "static const char *" can point to a different character constant because the pointer is mutable. However, if it is declared as type "static const char * const", the pointer will point to an immutable character constant, preventing it from being modified which can better ensure the safety and stability of the program. Fixes the below: WARNING: static const char * array should probably be static const char * const Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
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Darren Powell authored
split switch statement into two and consolidate the common code for printing most of the types of clock speeds Signed-off-by:
Darren Powell <darren.powell@amd.com> Reviewed-by:
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