Commit 56d6daa3 authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher
Browse files

drm/amdkfd: Fix reg offset for setting CWSR grace period 



This patch fixes the case where the code currently passes
absolute register address and not the reg offset, which HWS
expects, when sending the PM4 packet to set/update CWSR grace
period. Additionally, cleanup the signature of
build_grace_period_packet_info function as it no longer needs
the inst parameter.

Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Reviewed-by: default avatarJonathan Kim <jonathan.kim@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 88ca2f8a

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

+1 −2
Original line number Diff line number Diff line
@@ -980,8 +980,7 @@ void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev, 
						uint32_t wait_times,

						uint32_t grace_period,

						uint32_t *reg_offset,

						uint32_t *reg_data,

						uint32_t inst)

						uint32_t *reg_data)

{

	*reg_data = wait_times;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

+1 −2
Original line number Diff line number Diff line
@@ -55,5 +55,4 @@ void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev, 
					       uint32_t wait_times,

					       uint32_t grace_period,

					       uint32_t *reg_offset,

					       uint32_t *reg_data,

					       uint32_t inst);
 
					       uint32_t *reg_data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+2 −4
Original line number Diff line number Diff line
@@ -1103,8 +1103,7 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, 
		uint32_t wait_times,

		uint32_t grace_period,

		uint32_t *reg_offset,

		uint32_t *reg_data,

		uint32_t inst)

		uint32_t *reg_data)

{

	*reg_data = wait_times;
@@ -1120,8 +1119,7 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, 
			SCH_WAVE,

			grace_period);



	*reg_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

			mmCP_IQ_WAIT_TIME2);

	*reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);

}



void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

+1 −2
Original line number Diff line number Diff line
@@ -100,5 +100,4 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, 
					       uint32_t wait_times,

					       uint32_t grace_period,

					       uint32_t *reg_offset,

					       uint32_t *reg_data,

					       uint32_t inst);
 
					       uint32_t *reg_data);

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

+1 −2
Original line number Diff line number Diff line
@@ -1688,8 +1688,7 @@ static int start_cpsch(struct device_queue_manager *dqm) 
			dqm->dev->kfd2kgd->build_grace_period_packet_info(

					dqm->dev->adev,	dqm->wait_times,

					grace_period, &reg_offset,

					&dqm->wait_times,

					ffs(dqm->dev->xcc_mask) - 1);

					&dqm->wait_times);

	}



	dqm_unlock(dqm);