Commit e87a6c5b authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Blank phantom OTG before enabling 



[Description]
Before enabling the phantom OTG for an update we
must enable DPG to avoid underflow.

Reviewed-by: default avatarSamson Tam <samson.tam@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f4fa8fcd

drivers/gpu/drm/amd/display/dc/core/dc.c

+2 −48
Original line number Diff line number Diff line
@@ -1070,53 +1070,6 @@ static void apply_ctx_interdependent_lock(struct dc *dc, 
	}

}



static void phantom_pipe_blank(

		struct dc *dc,

		struct timing_generator *tg,

		int width,

		int height)

{

	struct dce_hwseq *hws = dc->hwseq;

	enum dc_color_space color_space;

	struct tg_color black_color = {0};

	struct output_pixel_processor *opp = NULL;

	uint32_t num_opps, opp_id_src0, opp_id_src1;

	uint32_t otg_active_width, otg_active_height;

	uint32_t i;



	/* program opp dpg blank color */

	color_space = COLOR_SPACE_SRGB;

	color_space_to_black_color(dc, color_space, &black_color);



	otg_active_width = width;

	otg_active_height = height;



	/* get the OPTC source */

	tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);

	ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);



	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {

		if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {

			opp = dc->res_pool->opps[i];

			break;

		}

	}



	if (opp && opp->funcs->opp_set_disp_pattern_generator)

		opp->funcs->opp_set_disp_pattern_generator(

				opp,

				CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,

				CONTROLLER_DP_COLOR_SPACE_UDEFINED,

				COLOR_DEPTH_UNDEFINED,

				&black_color,

				otg_active_width,

				otg_active_height,

				0);



	if (tg->funcs->is_tg_enabled(tg))

		hws->funcs.wait_for_blank_complete(opp);

}



static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

{

	if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
@@ -1207,7 +1160,8 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) 


					main_pipe_width = old_stream->mall_stream_config.paired_stream->dst.width;

					main_pipe_height = old_stream->mall_stream_config.paired_stream->dst.height;

					phantom_pipe_blank(dc, tg, main_pipe_width, main_pipe_height);

					if (dc->hwss.blank_phantom)

						dc->hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);

					tg->funcs->enable_crtc(tg);

				}

			}

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+9 −1
Original line number Diff line number Diff line
@@ -1840,10 +1840,18 @@ void dcn20_program_front_end_for_ctx( 
			dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {

			struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;



			if (tg->funcs->enable_crtc)

			if (tg->funcs->enable_crtc) {

				if (dc->hwss.blank_phantom) {

					int main_pipe_width, main_pipe_height;



					main_pipe_width = dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.paired_stream->dst.width;

					main_pipe_height = dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.paired_stream->dst.height;

					dc->hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);

				}

				tg->funcs->enable_crtc(tg);

			}

		}

	}

	/* OTG blank before disabling all front ends */

	for (i = 0; i < dc->res_pool->pipe_count; i++)

		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+46 −0
Original line number Diff line number Diff line
@@ -1573,3 +1573,49 @@ void dcn32_init_blank( 
	if (opp)

		hws->funcs.wait_for_blank_complete(opp);

}



void dcn32_blank_phantom(struct dc *dc,

		struct timing_generator *tg,

		int width,

		int height)

{

	struct dce_hwseq *hws = dc->hwseq;

	enum dc_color_space color_space;

	struct tg_color black_color = {0};

	struct output_pixel_processor *opp = NULL;

	uint32_t num_opps, opp_id_src0, opp_id_src1;

	uint32_t otg_active_width, otg_active_height;

	uint32_t i;



	/* program opp dpg blank color */

	color_space = COLOR_SPACE_SRGB;

	color_space_to_black_color(dc, color_space, &black_color);



	otg_active_width = width;

	otg_active_height = height;



	/* get the OPTC source */

	tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);

	ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);



	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {

		if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {

			opp = dc->res_pool->opps[i];

			break;

		}

	}



	if (opp && opp->funcs->opp_set_disp_pattern_generator)

		opp->funcs->opp_set_disp_pattern_generator(

				opp,

				CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,

				CONTROLLER_DP_COLOR_SPACE_UDEFINED,

				COLOR_DEPTH_UNDEFINED,

				&black_color,

				otg_active_width,

				otg_active_height,

				0);



	if (tg->funcs->is_tg_enabled(tg))

		hws->funcs.wait_for_blank_complete(opp);

}

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h

+5 −0
Original line number Diff line number Diff line
@@ -115,4 +115,9 @@ void dcn32_init_blank( 
		struct dc *dc,

		struct timing_generator *tg);



void dcn32_blank_phantom(struct dc *dc,

		struct timing_generator *tg,

		int width,

		int height);



#endif /* __DC_HWSS_DCN32_H__ */

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c

+1 −0
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = { 
	.update_phantom_vp_position = dcn32_update_phantom_vp_position,

	.update_dsc_pg = dcn32_update_dsc_pg,

	.apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom,

	.blank_phantom = dcn32_blank_phantom,

};



static const struct hwseq_private_funcs dcn32_private_funcs = {