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  1. Sep 24, 2021
  3. Aug 10, 2021
    • mergify[bot]'s avatar
      Fix Specification Memory Port Types (#2319) (#2320) · 3be34b2e
      mergify[bot] authored 
      

Correct incorrect type specified for memories in the FIRRTL
specification.  This is important because the memory type determines
what is a legal bundle to try to connect to a memory port.

I based this off of FIRRTL accepting the following circuit:

    circuit MemOrder:
      module MemOrder:
        input r: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip data : UInt<1>}
        input w: {addr : UInt<3>, en : UInt<1>, clk : Clock, data : UInt<1>, mask : UInt<1>}
        input rw: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip rdata : UInt<1>, wmode : UInt<1>, wdata : UInt<1>, wmask : UInt<1>}

        mem memory:
          data-type => UInt<1>
          depth => 8
          reader => r
          writer => w
          readwriter => rw
          read-latency => 1
          write-latency => 1
          read-under-write => undefined

        memory.r <= r
        memory.w <= w
        memory.rw <= rw

Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 8abf3085

)

# Conflicts:
#	spec/spec.pdf

Co-authored-by: default avatarSchuyler Eldridge <schuyler.eldridge@sifive.com>
      3be34b2e
  5. Aug 04, 2021
  7. Apr 16, 2021
    • mergify[bot]'s avatar
      Fix signedness of xor const prop with zero (#2179) (#2183) · 674a1bb4
      mergify[bot] authored 
      Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:

    circuit Foo :
      module Foo :
        input a: UInt<3>
        output b: UInt<4>
        b <= asUInt(xor(asSInt(a), SInt<4>(0)))

This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.

This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.

(cherry picked from commit e9b2946c

)

# Conflicts:
#	src/main/scala/firrtl/transforms/ConstantPropagation.scala

Co-authored-by: default avatarFabian Schuiki <fabian@schuiki.ch>
      674a1bb4
  9. Mar 27, 2021
  11. Mar 20, 2021
  13. Mar 14, 2021
    • mergify[bot]'s avatar
      Fix cat of zero-width SInt (bp #2116) (#2117) · 5ab6b20f
      mergify[bot] authored 
      * Fix cat of zero-width SInt (#2116)

Previously, concatenating two SInts where one is of zero-width would
return the non-zero-width SInt. This is incorrect because the output of
Cat should be of type UInt. Now the ZeroWidth transform will introduce a
cast when removing a Cat when the argument type is non-UInt.

(cherry picked from commit fd55c51b

)

# Conflicts:
#	src/main/scala/firrtl/passes/ZeroWidth.scala

* Fix merge conflicts

Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      5ab6b20f
  15. Jan 20, 2021
    • Jack Koenig's avatar
      Switch from Travis to Github Actions CI (#2041) (#2046) · b928a454
      Jack Koenig authored 
      * Fix .run_formal_checks for Github Actions instead of Travis
* Remove .run_chisel_tests

Because we publish SNAPSHOTs on every merge to master, the Chisel repo
checks against master of FIRRTL regularly

* Only run unidoc for Scala 2.12

Under Travis we ran for 2.11, 2.12, and 2.13, but it doesn't work when
using ++2.<major>.<minor> when major != to 2.12. It seems if we want to
run all 3, we have to run as `sbt +unidoc`. It's not clear how much
benefit we get from building on the other versions, so stick with 2.12
for now.

* Generate .mergify.yml with script in chisel-repo-tools

Generated with config:

conditions:
  - status-success=all tests passed
branches:
  - 1.2.x
  - 1.3.x
  - 1.4.x

(cherry picked from commit bbd7fc41)
      b928a454
  17. Dec 12, 2020
  19. Dec 08, 2020
  21. Dec 03, 2020
  23. Nov 24, 2020
  25. Nov 17, 2020
  27. Nov 14, 2020
  29. Oct 14, 2020
  31. Oct 13, 2020
  33. Oct 09, 2020
  35. Oct 01, 2020
  37. Sep 15, 2020
  39. Sep 11, 2020
  41. Aug 01, 2020
  43. Jul 31, 2020
  45. Jul 30, 2020
  47. Jul 16, 2020
    • mergify[bot]'s avatar
      Change ProtoBuf generated directory (bp #1762) (#1763) · c51126d2
      mergify[bot] authored 
      * Change ProtoBuf generated directory (#1762)

Changed from target/<scala-version>/src_managed/main/firrtl/ to
target/<scala-version>/src_managed/main/compiled_protobuf/firrtl/
The protobuf generation clears its target directory so it would clear
the generated ANTLR-generated files.

(cherry picked from commit c14330d6

)

# Conflicts:
#	build.sbt

* Fix for 1.2.x

Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      c51126d2
  49. Jun 26, 2020
  51. Jun 24, 2020
  53. Jun 11, 2020
  55. Jun 10, 2020
  57. Jun 07, 2020
  59. Jun 04, 2020