Pulling in the Zc chapter.

Pulling in the Zc chapter.

59 files changed, 4787 insertions, 4 deletions

diff --git a/src/riscv-unprivileged.adoc b/src/riscv-unprivileged.adoc
index 0743542..4a5bab8 100644
--- a/src/riscv-unprivileged.adoc
+++ b/src/riscv-unprivileged.adoc
@@ -127,7 +127,7 @@ include::zfa.adoc[]
 include::ztso-st-ext.adoc[]
 //ztso.tex
 include::rv-32-64g.adoc[]
-include::zc.adoc[]
+include::zc/Zc.adoc[]
 //gmaps.tex
 include::extending.adoc[]
 //extensions.tex
diff --git a/src/zc/.gitignore b/src/zc/.gitignore
new file mode 100644
index 0000000..feddacc
--- /dev/null
+++ b/src/zc/.gitignore
@@ -0,0 +1,4 @@
+*.svg
+.asciidoctor/
+
+
diff --git a/src/zc.adoc b/src/zc/Zc.adoc
index 0ec1b3e..137824f 100644
--- a/src/zc.adoc
+++ b/src/zc/Zc.adoc
@@ -1,6 +1,6 @@
-:sectnums:
-:version-label: v1.0.4-2
-:lifecycle-state: ratified
+//:sectnums:
+//:version-label: v1.0.4-2
+//:lifecycle-state: ratified
 
 [#Zc]
 == Zc* {version-label}
diff --git a/src/zc/Zcb_footer.adoc b/src/zc/Zcb_footer.adoc
new file mode 100644
index 0000000..1c8122d
--- /dev/null
+++ b/src/zc/Zcb_footer.adoc
@@ -0,0 +1,12 @@
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zcb (<<Zcb>>)
+|{version-label}
+|{lifecycle-state}
+|===
diff --git a/src/zc/Zcf_footer.adoc b/src/zc/Zcf_footer.adoc
new file mode 100644
index 0000000..62f336a
--- /dev/null
+++ b/src/zc/Zcf_footer.adoc
@@ -0,0 +1,12 @@
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zcf (<<Zcf>>)
+|{version-label}
+|{lifecycle-state}
+|===
diff --git a/src/zc/Zcmb_footer.adoc b/src/zc/Zcmb_footer.adoc
new file mode 100644
index 0000000..ac73f23
--- /dev/null
+++ b/src/zc/Zcmb_footer.adoc
@@ -0,0 +1,12 @@
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zcmb (<<Zcmb>>)
+|v0.70.5
+|{lifecycle-state}
+|===
diff --git a/src/zc/Zcmd.adoc b/src/zc/Zcmd.adoc
new file mode 100644
index 0000000..a5ff18e
--- /dev/null
+++ b/src/zc/Zcmd.adoc
@@ -0,0 +1,22 @@
+[#Zcmd]
+==== Zcmd v0.1
+
+This document is in the Development state. Assume everything can change. For more information see:
+https://riscv.org/spec-state
+
+[%header,cols="^1,^1,4,8"]
+|===
+|RV32
+|RV64
+|Mnemonic
+|Instruction
+
+|&#10003;
+|&#10003;
+|cm.decbnez t0, imm
+|<<#insns-cm_decbnez>> 
+
+|===
+
+include::cm_decbnez.adoc[]
+
diff --git a/src/zc/Zcmd.pdf b/src/zc/Zcmd.pdf
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diff --git a/src/zc/Zcmd_footer.adoc b/src/zc/Zcmd_footer.adoc
new file mode 100644
index 0000000..8fdcd87
--- /dev/null
+++ b/src/zc/Zcmd_footer.adoc
@@ -0,0 +1,12 @@
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zcmd (<<Zcmd>>)
+|0.1
+|Development
+|===
diff --git a/src/zc/Zcmp_footer.adoc b/src/zc/Zcmp_footer.adoc
new file mode 100644
index 0000000..b0d3d4a
--- /dev/null
+++ b/src/zc/Zcmp_footer.adoc
@@ -0,0 +1,12 @@
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zcmp (<<Zcmp>>)
+|{version-label}
+|{lifecycle-state}
+|===
diff --git a/src/zc/Zcmpe_footer.adoc b/src/zc/Zcmpe_footer.adoc
new file mode 100644
index 0000000..1e7ba38
--- /dev/null
+++ b/src/zc/Zcmpe_footer.adoc
@@ -0,0 +1,12 @@
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zcmpe (<<Zcmpe>>)
+|{version-label}
+|Stable
+|===
diff --git a/src/zc/Zcmt_footer.adoc b/src/zc/Zcmt_footer.adoc
new file mode 100644
index 0000000..5206794
--- /dev/null
+++ b/src/zc/Zcmt_footer.adoc
@@ -0,0 +1,12 @@
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zcmt (<<Zcmt>>)
+|{version-label}
+|{lifecycle-state}
+|===
diff --git a/src/zc/c_lbsb_imm_offset.adoc b/src/zc/c_lbsb_imm_offset.adoc
new file mode 100644
index 0000000..dd7bf83
--- /dev/null
+++ b/src/zc/c_lbsb_imm_offset.adoc
@@ -0,0 +1,8 @@
+
+The immediate offset is formed as follows:
+[source,sail]
+--
+  uimm[31:2] = 0;
+  uimm[1]    = encoding[5];
+  uimm[0]    = encoding[6];
+--
diff --git a/src/zc/c_lbu.adoc b/src/zc/c_lbu.adoc
new file mode 100644
index 0000000..3928373
--- /dev/null
+++ b/src/zc/c_lbu.adoc
@@ -0,0 +1,46 @@
+<<<
+[#insns-c_lbu,reftext="Load unsigned byte, 16-bit encoding"]
+=== c.lbu
+
+Synopsis::
+Load unsigned byte, 16-bit encoding
+
+Mnemonic::
+c.lbu _rd'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rd\'' },
+    { bits:  2, name: 'uimm[0|1]' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  3, name: 0x0 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+include::c_lbsb_imm_offset.adoc[]
+
+Description::
+This instruction loads a byte from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting byte is zero extended to XLEN bits and is written to _rd'_. 
+
+[NOTE]
+  _rd'_ and _rs1'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-lbu>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);
+--
+
+include::Zcb_footer.adoc[]
diff --git a/src/zc/c_lh.adoc b/src/zc/c_lh.adoc
new file mode 100644
index 0000000..e519754
--- /dev/null
+++ b/src/zc/c_lh.adoc
@@ -0,0 +1,48 @@
+<<<
+[#insns-c_lh,reftext="Load signed halfword, 16-bit encoding"]
+=== c.lh
+
+Synopsis::
+Load signed halfword, 16-bit encoding
+
+Mnemonic::
+c.lh _rd'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rd\'' },
+    { bits:  1, name: 'uimm[1]' },
+    { bits:  1, name: 0x1 },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  3, name: 0x1 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+include::c_lhsh_imm_offset.adoc[]
+
+Description::
+This instruction loads a halfword from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting halfword is sign extended to XLEN bits and is written to _rd'_. 
+
+[NOTE]
+  _rd'_ and _rs1'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-lh>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);
+--
+
+include::Zcb_footer.adoc[]
+
diff --git a/src/zc/c_lhsh_imm_offset.adoc b/src/zc/c_lhsh_imm_offset.adoc
new file mode 100644
index 0000000..20f1b2b
--- /dev/null
+++ b/src/zc/c_lhsh_imm_offset.adoc
@@ -0,0 +1,8 @@
+
+The immediate offset is formed as follows:
+[source,sail]
+--
+  uimm[31:2] = 0;
+  uimm[1]    = encoding[5];
+  uimm[0]    = 0;
+--
diff --git a/src/zc/c_lhu.adoc b/src/zc/c_lhu.adoc
new file mode 100644
index 0000000..6db5211
--- /dev/null
+++ b/src/zc/c_lhu.adoc
@@ -0,0 +1,48 @@
+<<<
+[#insns-c_lhu,reftext="Load unsigned halfword, 16-bit encoding"]
+=== c.lhu
+
+Synopsis::
+Load unsigned halfword, 16-bit encoding
+
+Mnemonic::
+c.lhu _rd'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rd\'' },
+    { bits:  1, name: 'uimm[1]' },
+    { bits:  1, name: 0x0 },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  3, name: 0x1 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+include::c_lhsh_imm_offset.adoc[]
+
+Description::
+This instruction loads a halfword from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting halfword is zero extended to XLEN bits and is written to _rd'_. 
+
+[NOTE]
+  _rd'_ and _rs1'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-lhu>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);
+--
+
+include::Zcb_footer.adoc[]
+
diff --git a/src/zc/c_mul.adoc b/src/zc/c_mul.adoc
new file mode 100644
index 0000000..d2f5a21
--- /dev/null
+++ b/src/zc/c_mul.adoc
@@ -0,0 +1,48 @@
+<<<
+[#insns-c_mul,reftext="Multiply, 16-bit encoding"]
+=== c.mul
+
+Synopsis::
+Multiply, 16-bit encoding
+
+Mnemonic::
+c.mul _rsd'_, _rs2'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x1, attr: ['C1'] },
+    { bits:  3, name: 'rs2\'', attr: ['SRC2']  },
+    { bits:  2, name: 0x2, attr: ['FUNCT2'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
+    { bits:  3, name: 0x7 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Description::
+This instruction multiplies XLEN bits of the source operands from _rsd'_ and _rs2'_ and writes the lowest XLEN bits of the result to _rsd'_.
+
+[NOTE]
+  _rd'/rs1'_ and _rs2'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+M or Zmmul must be configured.
+
+32-bit equivalent::
+<<insns-mul>>
+
+[NOTE]
+
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_, and for _rs2'_ is called _rs2c_.
+
+Operation::
+[source,sail]
+--
+let result_wide = to_bits(2 * sizeof(xlen), signed(X(rsdc)) * signed(X(rs2c)));
+X(rsdc) = result_wide[(sizeof(xlen) - 1) .. 0];
+--
+
+include::Zcb_footer.adoc[]
+
diff --git a/src/zc/c_not.adoc b/src/zc/c_not.adoc
new file mode 100644
index 0000000..4207ba0
--- /dev/null
+++ b/src/zc/c_not.adoc
@@ -0,0 +1,50 @@
+<<<
+[#insns-c_not,reftext="Bitwise not, 16-bit encoding"]
+=== c.not
+
+Synopsis::
+Bitwise not, 16-bit encoding
+
+Mnemonic::
+c.not _rd'/rs1'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x1, attr: ['C1'] },
+    { bits:  3, name: 0x5, attr: ['C.NOT'] },
+    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
+    { bits:  3, name: 0x7 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Description::
+This instruction takes the one's complement of _rd'/rs1'_ and writes the result to the same register.
+
+[NOTE]
+  _rd'/rs1'_ is from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+[source,sail]
+--
+xori rd'/rs1', rd'/rs1', -1
+--
+
+[NOTE]
+
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.
+
+Operation::
+[source,sail]
+--
+X(rsdc) = X(rsdc) XOR -1;
+--
+
+include::Zcb_footer.adoc[]
+
diff --git a/src/zc/c_sb.adoc b/src/zc/c_sb.adoc
new file mode 100644
index 0000000..d0b1ac6
--- /dev/null
+++ b/src/zc/c_sb.adoc
@@ -0,0 +1,46 @@
+<<<
+[#insns-c_sb,reftext="Store byte, 16-bit encoding"]
+=== c.sb
+
+Synopsis::
+Store byte, 16-bit encoding
+
+Mnemonic::
+c.sb _rs2'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rs2\'' },
+    { bits:  2, name: 'uimm[0|1]' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  3, name: 0x2 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+include::c_lbsb_imm_offset.adoc[]
+
+Description::
+This instruction stores the least significant byte of _rs2'_ to the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. 
+
+[NOTE]
+  _rs1'_ and _rs2'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-sb>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)
+--
+
+include::Zcb_footer.adoc[]
diff --git a/src/zc/c_sext_b.adoc b/src/zc/c_sext_b.adoc
new file mode 100644
index 0000000..bcf8f15
--- /dev/null
+++ b/src/zc/c_sext_b.adoc
@@ -0,0 +1,48 @@
+<<<
+[#insns-c_sext_b,reftext="Sign extend byte, 16-bit encoding"]
+=== c.sext.b
+
+Synopsis::
+Sign extend byte, 16-bit encoding
+
+Mnemonic::
+c.sext.b _rd'/rs1'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x1, attr: ['C1'] },
+    { bits:  3, name: 0x1, attr: ['C.SEXT.B'] },
+    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
+    { bits:  3, name: 0x7 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Description::
+This instruction takes a single source/destination operand. 
+It sign-extends the least-significant byte in the operand to XLEN bits by copying the most-significant bit
+in the byte (i.e., bit 7) to all of the more-significant bits.
+
+[NOTE]
+  _rd'/rs1'_ is from the standard 8-register set x8-x15.
+
+Prerequisites::
+Zbb is also required.
+
+32-bit equivalent::
+<<insns-sext_b>> from Zbb
+
+[NOTE]
+
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.
+
+Operation::
+[source,sail]
+--
+X(rsdc) = EXTS(X(rsdc)[7..0]);
+--
+
+include::Zcb_footer.adoc[]
diff --git a/src/zc/c_sext_h.adoc b/src/zc/c_sext_h.adoc
new file mode 100644
index 0000000..82a64db
--- /dev/null
+++ b/src/zc/c_sext_h.adoc
@@ -0,0 +1,49 @@
+<<<
+[#insns-c_sext_h,reftext="Sign extend halfword, 16-bit encoding"]
+=== c.sext.h
+
+Synopsis::
+Sign extend halfword, 16-bit encoding
+
+Mnemonic::
+c.sext.h _rd'/rs1'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x1, attr: ['C1'] },
+    { bits:  3, name: 0x3, attr: ['C.SEXT.H'] },
+    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
+    { bits:  3, name: 0x7 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Description::
+This instruction takes a single source/destination operand. 
+It sign-extends the least-significant halfword in the operand to XLEN bits by copying the most-significant bit
+in the halfword (i.e., bit 15) to all of the more-significant bits.
+
+[NOTE]
+  _rd'/rs1'_ is from the standard 8-register set x8-x15.
+
+Prerequisites::
+Zbb is also required.
+
+32-bit equivalent::
+<<insns-sext_h>> from Zbb
+
+[NOTE]
+
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.
+
+Operation::
+[source,sail]
+--
+X(rsdc) = EXTS(X(rsdc)[15..0]);
+--
+
+include::Zcb_footer.adoc[]
+
diff --git a/src/zc/c_sh.adoc b/src/zc/c_sh.adoc
new file mode 100644
index 0000000..977a887
--- /dev/null
+++ b/src/zc/c_sh.adoc
@@ -0,0 +1,48 @@
+<<<
+[#insns-c_sh,reftext="Store halfword, 16-bit encoding"]
+=== c.sh
+
+Synopsis::
+Store halfword, 16-bit encoding
+
+Mnemonic::
+c.sh _rs2'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rs2\'' },
+    { bits:  1, name: 'uimm[1]' },
+    { bits:  1, name: '0' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  3, name: 0x3 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+include::c_lhsh_imm_offset.adoc[]
+
+Description::
+This instruction stores the least significant halfword of _rs2'_ to the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. 
+
+[NOTE]
+  _rs1'_ and _rs2'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-sh>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c)
+--
+
+include::Zcb_footer.adoc[]
+
diff --git a/src/zc/c_zca_required.adoc b/src/zc/c_zca_required.adoc
new file mode 100644
index 0000000..f7b460c
--- /dev/null
+++ b/src/zc/c_zca_required.adoc
diff --git a/src/zc/c_zext_b.adoc b/src/zc/c_zext_b.adoc
new file mode 100644
index 0000000..500461d
--- /dev/null
+++ b/src/zc/c_zext_b.adoc
@@ -0,0 +1,52 @@
+<<<
+[#insns-c_zext_b,reftext="Zero extend byte, 16-bit encoding"]
+=== c.zext.b
+
+Synopsis::
+Zero extend byte, 16-bit encoding
+
+Mnemonic::
+c.zext.b _rd'/rs1'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x1, attr: ['C1'] },
+    { bits:  3, name: 0x0, attr: ['C.ZEXT.B'] },
+    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
+    { bits:  3, name: 0x7 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Description::
+This instruction takes a single source/destination operand. 
+It zero-extends the least-significant byte of the operand to XLEN bits by inserting zeros into all of
+the bits more significant than 7.
+
+[NOTE]
+  _rd'/rs1'_ is from the standard 8-register set x8-x15.  
+
+Prerequisites::
+None
+
+32-bit equivalent::
+[source,sail]
+--
+andi rd'/rs1', rd'/rs1', 0xff
+--
+
+[NOTE]
+
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.
+
+Operation::
+[source,sail]
+--
+X(rsdc) = EXTZ(X(rsdc)[7..0]);
+--
+
+include::Zcb_footer.adoc[]
+
diff --git a/src/zc/c_zext_h.adoc b/src/zc/c_zext_h.adoc
new file mode 100644
index 0000000..5999857
--- /dev/null
+++ b/src/zc/c_zext_h.adoc
@@ -0,0 +1,49 @@
+<<<
+[#insns-c_zext_h,reftext="Zero extend halfword, 16-bit encoding"]
+=== c.zext.h
+
+Synopsis::
+Zero extend halfword, 16-bit encoding
+
+Mnemonic::
+c.zext.h _rd'/rs1'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x1, attr: ['C1'] },
+    { bits:  3, name: 0x2, attr: ['C.ZEXT.H'] },
+    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
+    { bits:  3, name: 0x7 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Description::
+This instruction takes a single source/destination operand. 
+It zero-extends the least-significant halfword of the operand to XLEN bits by inserting zeros into all of
+the bits more significant than 15.
+
+[NOTE]
+  _rd'/rs1'_ is from the standard 8-register set x8-x15.
+
+Prerequisites::
+Zbb is also required.
+
+32-bit equivalent::
+<<insns-zext_h>> from Zbb
+
+[NOTE]
+
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.
+
+Operation::
+[source,sail]
+--
+X(rsdc) = EXTZ(X(rsdc)[15..0]);
+--
+
+include::Zcb_footer.adoc[]
+
diff --git a/src/zc/c_zext_w.adoc b/src/zc/c_zext_w.adoc
new file mode 100644
index 0000000..3540405
--- /dev/null
+++ b/src/zc/c_zext_w.adoc
@@ -0,0 +1,51 @@
+<<<
+[#insns-c_zext_w,reftext="Zero extend word, 16-bit encoding"]
+=== c.zext.w
+
+Synopsis::
+Zero extend word, 16-bit encoding
+
+Mnemonic::
+c.zext.w _rd'/rs1'_
+
+Encoding (RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x1, attr: ['C1'] },
+    { bits:  3, name: 0x4, attr: ['C.ZEXT.W'] },
+    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
+    { bits:  3, name: 0x7 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Description::
+This instruction takes a single source/destination operand. 
+It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of
+the bits more significant than 31.
+
+[NOTE]
+  _rd'/rs1'_ is from the standard 8-register set x8-x15.
+
+Prerequisites::
+Zba is also required.
+ 
+32-bit equivalent::
+[source,sail]
+--
+add.uw rd'/rs1', rd'/rs1', zero
+--
+
+[NOTE]
+
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.
+
+Operation::
+[source,sail]
+--
+X(rsdc) = EXTZ(X(rsdc)[31..0]);
+--
+
+include::Zcb_footer.adoc[]
diff --git a/src/zc/changes_since_v0.50.adoc b/src/zc/changes_since_v0.50.adoc
new file mode 100644
index 0000000..a4452b1
--- /dev/null
+++ b/src/zc/changes_since_v0.50.adoc
@@ -0,0 +1,130 @@
+
+There are many changes since v0.50.1, which has been used for toolchain, spike, qemu and the CV32E41P implementation.
+
+The status of all of the instructions are in the tables. Note that _all_ subsets have been redefined.
+
+= Load/store
+
+.Load/store
+[options="header",width=100%]
+|====================================================================================
+| v0.50 name | v0.70 Name | Encoding changed? | Semantics changed? | Notes
+| C.LB       | CM.LB      | Y                 | N                  | uimm < 4 is "custom defined"
+| C.LBU      | CM.LBU     | Y                 | N                  | uimm < 4 is "custom defined"
+| C.LH       | CM.LH      | Y                 | N                  | uimm < 4 is "custom defined"
+| C.LHU      | CM.LHU     | Y                 | N                  | uimm < 4 is "custom defined"
+| C.SB       | CM.SB      | Y                 | N                  | uimm < 4 is "custom defined"
+| C.SH       | CM.SH      | Y                 | N                  | uimm < 4 is "custom defined"
+| N/A        | C.LBU      | N/A               | N/A                | CM.LBU with shorter uimm
+| N/A        | C.LH       | N/A               | N/A                | CM.LH  with shorter uimm
+| N/A        | C.LHU      | N/A               | N/A                | CM.LHU with shorter uimm
+| N/A        | C.SB       | N/A               | N/A                | CM.SB  with shorter uimm
+| N/A        | C.SH       | N/A               | N/A                | CM.SH  with shorter uimm
+|====================================================================================
+
+= Table jump
+
+.Table Jump
+[options="header",width=100%]
+|====================================================================================
+| v0.50 name | v0.70 Name | Encoding changed? | Semantics changed? | Notes
+| C.TBLJAL   | CM.JALT    | Y                 | Y - exception model| Meaning of table index changed in the encoding, # removed from assembly syntax
+| C.TBLJ     | CM.J       | Y                 | Y - exception model| Meaning of table index changed in the encoding, # removed from assembly syntax
+| C.TBLJALM  | N/A        | N/A               | N/A                | Deleted
+|====================================================================================
+
+See this [commit](https://github.com/riscv/riscv-code-size-reduction/commit/8ba5b0fdf05d6fd5af118ba5301910d049abd1a8#diff-8d03bd23cf9ec0eb75984f7c6d4181aa9548acb5898dc9159514e24398076836) for the change in the table jump exception model.
+
+= Double move
+
+.Double move
+[options="header",width=100%]
+|====================================================================================
+| v0.50 name | v0.70 Name | Encoding changed? | Semantics changed? | Notes
+| C.MVA01S07 | CM.MVA01S  | Y                 | N                  |
+| N/A        | CM.MVSA01  | N/A               | N/A                | New instruction
+|====================================================================================
+
+Note that the .E extension versions for the EABI will be specified in the future, and cannot yet be confirmed as the EABI is not frozen.
+
+= Simple instructions
+
+.Simple instructions
+[options="header",width=100%]
+|====================================================================================
+| v0.50 name | v0.70 Name | Encoding changed? | Semantics changed? | Notes
+| C.ZEXT.B   | same       | Y                 | N                  |
+| C.ZEXT.H   | same       | Y                 | N                  |
+| C.SEXT.B   | same       | Y                 | N                  |
+| C.SEXT.H   | same       | Y                 | N                  |
+| C.SEXT.W   | same       | Y                 | N                  |
+| C.NOT      | same       | Y                 | N                  |
+| C.MUL      | same       | N                 | N                  | unchanged
+|====================================================================================
+
+= Push/pop
+
+All 32-bit forms are removed and all the 16-bit forms support 12 register lists (excluding {ra, s0-s10}):
+
+. {ra}
+. {ra, s0}
+. {ra, s0-s1}
+. {ra, s0-s2}
+. {ra, s0-s3}
+. {ra, s0-s4}
+. {ra, s0-s5}
+. {ra, s0-s6}
+. {ra, s0-s7}
+. {ra, s0-s8}
+. {ra, s0-s9}
+. {ra, s0-s11}
+
+spimm length also updated.
+
+Note that the .E extension versions for the EABI will be specified in the future, and cannot yet be confirmed as the EABI is not frozen.
+
+.Push/pop instructions
+[options="header",width=100%]
+|====================================================================================
+| v0.50 name | v0.70 Name | Encoding changed? | Semantics changed? | Notes
+| C.PUSH     | CM.PUSH    | Y                 | Y                  | areg_list no longer supported
+| C.POP      | CM.POP     | Y                 | Y                  | 
+| C.POPRET   | CM.POPRET  | Y                 | Y                  | CM.POPRET doesn't return a value
+| C.POPRET   | CM.POPRETZ | Y                 | Y                  | separate encoding for return zero
+|====================================================================================
+
+= Instructions in v0.50 but *not* in v0.70
+
+These instructions can be left in the compiler as experimental, enabled with the following switches:
+
+[#compilerswitches]
+.Compiler switches experimental instructions
+[options="header",width=100%]
+|==============================================================================
+| Switch             | Enabled instructions
+| -mzce-lsgp         | LWGP, SWGP, LDGP (RV64), SDGP (RV64)
+| -mzce-muli         | MULI
+| -mzce-beqi         | BEQI
+| -mzce-bnei         | BNEI
+| -mzce-cdecbnez     | C.DECBNEZ
+| -mzce-decbnez      | DECBNEZ
+|==============================================================================
+
+== 16-bit Instructions
+
+C.DECBNEZ - the encoding space for this has been used by all the CM.* instructions.
+Therefore this instruction must be disabled in the compiler - unless an encoding is proposed.
+
+C.NEG - this is not very useful and can be deleted.
+
+== 32-bit Instructions
+
+MULI - This is in custom-0, so can be kept unchanged. Early benchmarking results suggest it's not much use, and the encoding is expensive so it's unlikely to ever be included in an extension.
+
+BEQI, BNEI - these fill in the 2 gaps in the BRANCH encoding group - these encodings have not been allocated to other instructions, so these can stay unchanged
+
+DECBNEZ - this should be updated to match https://github.com/riscv/riscv-code-size-reduction/blob/master/Zce-release-candidate/Zcmd.pdf
+
+LWGP, SWGP, LDGP, SDGP - these overlap with C.FLD, C.FSD
+
+PUSH/POP/POPRET - delete all of these
diff --git a/src/zc/cm_decbnez.adoc b/src/zc/cm_decbnez.adoc
new file mode 100644
index 0000000..912b768
--- /dev/null
+++ b/src/zc/cm_decbnez.adoc
@@ -0,0 +1,50 @@
+<<<
+[#insns-cm_decbnez,reftext="Decrement and branch, 16-bit encoding"]
+=== cm.decbnez: This is in the _development_ phase, for benchmarking and prototyping only
+
+Synopsis::
+Decrement and branch, 16-bit encoding
+
+Mnemonic::
+cm.decbnez _t0_, _offset_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,              attr: ['C2'] },
+    { bits:  6, name: 'imm[6|7|3:1|5]', attr: [] },
+    { bits:  1, name: 0x1,              attr: [] },
+    { bits:  3, name: 'imm[4|9:8]',     attr: [] },
+    { bits:  1, name: 0x1,              attr: [] },
+    { bits:  3, name: 0x5,              attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+
+  In the current proposal only t0 can be decremented, future versions may allow more registers
+
+Description::
+This instruction decrements _t0_, and increments the PC by the sign extended immediate if _t0_ is zero *after* the decrement.
+
+Prerequisites::
+C or Zca
+
+32-bit equivalent::
+None
+
+Operation::
+[source,sail]
+--
+
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+t0 = 5;
+X(t0) = X(t0)-1;
+if (X(t0)==0) PC+=sext(imm); else PC+=2;
+
+--
+
+include::Zcmd_footer.adoc[]
+
diff --git a/src/zc/cm_jalt.adoc b/src/zc/cm_jalt.adoc
new file mode 100644
index 0000000..372d933
--- /dev/null
+++ b/src/zc/cm_jalt.adoc
@@ -0,0 +1,74 @@
+<<<
+[#insns-cm_jalt,reftext="Jump and link via table"]
+=== cm.jalt
+
+Synopsis::
+jump via table with optional link
+
+Mnemonic::
+cm.jalt _index_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,      attr: ['C2'] },
+    { bits:  8, name: 'index',  attr: [] },
+    { bits:  3, name: 0x0,      attr: [] },
+    { bits:  3, name: 0x5,      attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+
+  For this encoding to decode as _cm.jalt_, _index>=32_, otherwise it decodes as _cm.jt_, see <<insns-cm_jt>>.
+
+[NOTE]
+
+  If JVT.mode = 0 (Jump Table Mode) then _cm.jalt_ behaves as specified here. If JVT.mode is a reserved value, then _cm.jalt_ is also reserved. In the future other defined values of JVT.mode may change the behaviour of _cm.jalt_.
+
+Assembly Syntax::
+
+[source,sail]
+--
+cm.jalt index
+--
+
+Description::
+
+_cm.jalt_ reads an entry from the jump vector table in memory and jumps to the address that was read, linking to _ra_.
+
+For further information see <<insns-tablejump>>.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+No direct equivalent encoding exists.
+
+<<<
+
+[#insns-cm_jalt-SAIL,reftext="cm.jalt SAIL code"]
+Operation::
+
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+# target_address is temporary internal state, it doesn't represent a real register
+# InstMemory is byte indexed
+
+switch(XLEN) {
+  32:  table_address[XLEN-1:0] = JVT.base + (index<<2);
+  64:  table_address[XLEN-1:0] = JVT.base + (index<<3);
+}
+
+//fetch from the jump table
+target_address[XLEN-1:0] = InstMemory[table_address][XLEN-1:0];
+
+jal ra, target_address[XLEN-1:0]&~0x1;
+
+--
+
+include::Zcmt_footer.adoc[]
+
diff --git a/src/zc/cm_jt.adoc b/src/zc/cm_jt.adoc
new file mode 100644
index 0000000..8c7f67d
--- /dev/null
+++ b/src/zc/cm_jt.adoc
@@ -0,0 +1,74 @@
+<<<
+[#insns-cm_jt,reftext="Jump via table"]
+=== cm.jt
+
+Synopsis::
+jump via table
+
+Mnemonic::
+cm.jt _index_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,      attr: ['C2'] },
+    { bits:  8, name: 'index',  attr: [] },
+    { bits:  3, name: 0x0,      attr: [] },
+    { bits:  3, name: 0x5,      attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+
+  For this encoding to decode as _cm.jt_, _index<32_, otherwise it decodes as _cm.jalt_, see <<insns-cm_jalt>>.
+
+[NOTE]
+
+  If JVT.mode = 0 (Jump Table Mode) then _cm.jt_ behaves as specified here. If JVT.mode is a reserved value, then _cm.jt_ is also reserved. In the future other defined values of JVT.mode may change the behaviour of _cm.jt_.
+
+Assembly Syntax::
+
+[source,sail]
+--
+cm.jt index
+--
+
+Description::
+
+_cm.jt_ reads an entry from the jump vector table in memory and jumps to the address that was read.
+
+For further information see <<insns-tablejump>>.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+No direct equivalent encoding exists.
+
+<<<
+
+[#insns-cm_jt-SAIL,reftext="cm.jt SAIL code"]
+Operation::
+
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+# target_address is temporary internal state, it doesn't represent a real register
+# InstMemory is byte indexed
+
+switch(XLEN) {
+  32:  table_address[XLEN-1:0] = JVT.base + (index<<2);
+  64:  table_address[XLEN-1:0] = JVT.base + (index<<3);
+}
+
+//fetch from the jump table
+target_address[XLEN-1:0] = InstMemory[table_address][XLEN-1:0];
+
+j target_address[XLEN-1:0]&~0x1;
+
+--
+
+include::Zcmt_footer.adoc[]
+
diff --git a/src/zc/cm_lb.adoc b/src/zc/cm_lb.adoc
new file mode 100644
index 0000000..525ba97
--- /dev/null
+++ b/src/zc/cm_lb.adoc
@@ -0,0 +1,47 @@
+<<<
+[#insns-cm_lb,reftext="Load signed byte, 16-bit encoding"]
+=== cm.lb
+
+Synopsis::
+Load signed byte, 16-bit encoding
+
+Mnemonic::
+cm.lb _rd'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rd\'' },
+    { bits:  2, name: 'uimm[2:1]' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  2, name: 'uimm[0|3]' },
+    { bits:  1, name: 0x0 },
+    { bits:  3, name: 0x1, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+include::cm_lbsb_imm_offset.adoc[]
+
+Description::
+This instruction loads a byte from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting byte is sign extended to XLEN bits and is written to _rd'_. 
+
+[NOTE]
+  _rd'_ and _rs1'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-lb>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+X(rdc) = EXTS(mem[X(rs1c)+EXTZ(uimm)][7..0]);
+--
+
+include::Zcmb_footer.adoc[]
diff --git a/src/zc/cm_lbsb_imm_offset.adoc b/src/zc/cm_lbsb_imm_offset.adoc
new file mode 100644
index 0000000..4df7702
--- /dev/null
+++ b/src/zc/cm_lbsb_imm_offset.adoc
@@ -0,0 +1,9 @@
+
+The immediate offset is formed as follows:
+[source,sail]
+--
+  uimm[31:4] = 0;
+  uimm[3]    = encoding[10];
+  uimm[2:1]  = encoding[6:5];
+  uimm[0]    = encoding[11];
+--
diff --git a/src/zc/cm_lbu.adoc b/src/zc/cm_lbu.adoc
new file mode 100644
index 0000000..7e9735f
--- /dev/null
+++ b/src/zc/cm_lbu.adoc
@@ -0,0 +1,50 @@
+<<<
+[#insns-cm_lbu,reftext="Load unsigned byte, 16-bit encoding"]
+=== cm.lbu
+
+Synopsis::
+Load unsigned byte, 16-bit encoding
+
+Mnemonic::
+cm.lbu _rd'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2, attr: ['C2'] },
+    { bits:  3, name: 'rd\'' },
+    { bits:  2, name: 'uimm[2:1]' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  2, name: 'uimm[0|3]' },
+    { bits:  1, name: 0x0 },
+    { bits:  3, name: 0x1, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+  If _uimm < 4_ the encoding is designated for custom use, as the functionality overlaps with <<insns-c_lbu>>.
+
+include::cm_lbsb_imm_offset.adoc[]
+
+Description::
+This instruction loads a byte from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting byte is zero extended to XLEN bits and is written to _rd'_. 
+
+[NOTE]
+  _rd'_ and _rs1'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-lbu>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);
+--
+
+include::Zcmb_footer.adoc[]
diff --git a/src/zc/cm_lh.adoc b/src/zc/cm_lh.adoc
new file mode 100644
index 0000000..bb1b6b9
--- /dev/null
+++ b/src/zc/cm_lh.adoc
@@ -0,0 +1,51 @@
+<<<
+[#insns-cm_lh,reftext="Load signed halfword, 16-bit encoding"]
+=== cm.lh
+
+Synopsis::
+Load signed halfword, 16-bit encoding
+
+Mnemonic::
+cm.lh _rd'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rd\'' },
+    { bits:  2, name: 'uimm[2:1]' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  2, name: 'uimm[4:3]' },
+    { bits:  1, name: 0x1 },
+    { bits:  3, name: 0x1, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+  If _uimm < 4_ the encoding is designated for custom use, as the functionality overlaps with <<insns-c_lh>>.
+
+include::cm_lhsh_imm_offset.adoc[]
+
+Description::
+This instruction loads a halfword from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting halfword is sign extended to XLEN bits and is written to _rd'_. 
+
+[NOTE]
+  _rd'_ and _rs1'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-lh>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);
+--
+
+include::Zcmb_footer.adoc[]
+
diff --git a/src/zc/cm_lhsh_imm_offset.adoc b/src/zc/cm_lhsh_imm_offset.adoc
new file mode 100644
index 0000000..1aa6bc8
--- /dev/null
+++ b/src/zc/cm_lhsh_imm_offset.adoc
@@ -0,0 +1,9 @@
+
+The immediate offset is formed as follows:
+[source,sail]
+--
+  uimm[31:5] = 0;
+  uimm[4:3]  = encoding[11:10];
+  uimm[2:1]  = encoding[6:5];
+  uimm[0]    = 0;
+--
diff --git a/src/zc/cm_lhu.adoc b/src/zc/cm_lhu.adoc
new file mode 100644
index 0000000..3a3c281
--- /dev/null
+++ b/src/zc/cm_lhu.adoc
@@ -0,0 +1,51 @@
+<<<
+[#insns-cm_lhu,reftext="Load unsigned halfword, 16-bit encoding"]
+=== cm.lhu
+
+Synopsis::
+Load unsigned halfword, 16-bit encoding
+
+Mnemonic::
+cm.lhu _rd'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2, attr: ['C2'] },
+    { bits:  3, name: 'rd\'' },
+    { bits:  2, name: 'uimm[2:1]' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  2, name: 'uimm[4:3]' },
+    { bits:  1, name: 0x1 },
+    { bits:  3, name: 0x1, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+  If _uimm < 4_ the encoding is designated for custom use, as the functionality overlaps with <<insns-c_lhu>>.
+
+include::cm_lhsh_imm_offset.adoc[]
+
+Description::
+This instruction loads a halfword from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting halfword is zero extended to XLEN bits and is written to _rd'_. 
+
+[NOTE]
+  _rd'_ and _rs1'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-lhu>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);
+--
+
+include::Zcmb_footer.adoc[]
+
diff --git a/src/zc/cm_mva01s.adoc b/src/zc/cm_mva01s.adoc
new file mode 100644
index 0000000..9d36688
--- /dev/null
+++ b/src/zc/cm_mva01s.adoc
@@ -0,0 +1,62 @@
+<<<
+[#insns-cm_mva01s,reftext="Move two s0-s7 registers into a0-a1"]
+=== cm.mva01s
+
+Synopsis::
+Move two s0-s7 registers into a0-a1
+
+Mnemonic::
+cm.mva01s _r1s'_, _r2s'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,      attr: ['C2'] },
+    { bits:  3, name: 'r2s\'',  attr: [] },
+    { bits:  2, name: 0x3,      attr: [] },
+    { bits:  3, name: 'r1s\'',  attr: [] },
+    { bits:  3, name: 0x3,      attr: [] },
+    { bits:  3, name: 0x5,      attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Assembly Syntax::
+
+[source,sail]
+--
+cm.mva01s r1s', r2s'
+--
+
+Description::
+This instruction moves _r1s'_ into _a0_ and _r2s'_ into _a1_. 
+The execution is atomic, so it is not possible to observe state where only one of _a0_ or _a1_ have been updated.
+
+The encoding uses _sreg_ number specifiers instead of _xreg_ number specifiers to save encoding space. 
+The mapping between them is specified in the pseudo-code below.
+
+[NOTE]
+
+  The _s_ register mapping is taken from the UABI, and may not match the currently unratified EABI. _cm.mva01s.e_ may be included in the future.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+No direct equivalent encoding exists.
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+if (RV32E && (r1sc>1 || r2sc>1)) {
+  reserved();
+}
+xreg1 = {r1sc[2:1]>0,r1sc[2:1]==0,r1sc[2:0]};
+xreg2 = {r2sc[2:1]>0,r2sc[2:1]==0,r2sc[2:0]};
+X[10] = X[xreg1];
+X[11] = X[xreg2];
+--
+
+include::Zcmp_footer.adoc[]
+
diff --git a/src/zc/cm_mvsa01.adoc b/src/zc/cm_mvsa01.adoc
new file mode 100644
index 0000000..fd59c85
--- /dev/null
+++ b/src/zc/cm_mvsa01.adoc
@@ -0,0 +1,65 @@
+<<<
+[#insns-cm_mvsa01,reftext="Move a0-a1 into two different s0-s7 registers"]
+=== cm.mvsa01
+
+Synopsis::
+Move a0-a1 into two registers of s0-s7
+
+Mnemonic::
+cm.mvsa01 _r1s'_, _r2s'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,      attr: ['C2'] },
+    { bits:  3, name: 'r2s\'',  attr: [] },
+    { bits:  2, name: 0x1,      attr: [] },
+    { bits:  3, name: 'r1s\'',  attr: [] },
+    { bits:  3, name: 0x3,      attr: [] },
+    { bits:  3, name: 0x5,      attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+  For the encoding to be legal _r1s'_ != _r2s'_.
+
+Assembly Syntax::
+
+[source,sail]
+--
+cm.mvsa01 r1s', r2s'
+--
+
+Description::
+This instruction moves _a0_ into _r1s'_ and _a1_ into _r2s'_.  _r1s'_ and _r2s'_ must be different.
+The execution is atomic, so it is not possible to observe state where only one of _r1s'_ or _r2s'_ has been updated.
+
+The encoding uses _sreg_ number specifiers instead of _xreg_ number specifiers to save encoding space. 
+The mapping between them is specified in the pseudo-code below.
+
+[NOTE]
+
+  The _s_ register mapping is taken from the UABI, and may not match the currently unratified EABI. _cm.mvsa01.e_ may be included in the future.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+No direct equivalent encoding exists.
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+if (RV32E && (r1sc>1 || r2sc>1)) {
+  reserved();
+}
+xreg1 = {r1sc[2:1]>0,r1sc[2:1]==0,r1sc[2:0]};
+xreg2 = {r2sc[2:1]>0,r2sc[2:1]==0,r2sc[2:0]};
+X[xreg1] = X[10];
+X[xreg2] = X[11];
+--
+
+include::Zcmp_footer.adoc[]
+
diff --git a/src/zc/cm_pop.adoc b/src/zc/cm_pop.adoc
new file mode 100644
index 0000000..30e097e
--- /dev/null
+++ b/src/zc/cm_pop.adoc
@@ -0,0 +1,49 @@
+<<<
+[#insns-cm_pop,reftext="Pop registers, deallocate stack frame."]
+=== cm.pop
+
+Synopsis::
+Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.
+
+Mnemonic::
+cm.pop  _{reg_list}, stack_adj_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,             attr: ['C2'] },
+    { bits:  2, name: 'spimm\[5:4\]',  attr: [] },
+    { bits:  4, name: 'rlist',         attr: [] },
+    { bits:  5, name: 0x1a,            attr: [] },
+    { bits:  3, name: 0x5,             attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+
+  _rlist_ values 0 to 3 are reserved for a future EABI variant called _cm.pop.e_
+
+Assembly Syntax::
+
+[source,sail]
+--
+cm.pop {reg_list},  stack_adj
+cm.pop {xreg_list}, stack_adj
+--
+
+include::variable_def.adoc[]
+include::pushpop_vars.adoc[]
+
+<<<
+
+Description::
+This instruction pops (loads) the registers in _reg_list_ from stack memory, 
+and then adjusts the stack pointer by _stack_adj_. 
+
+include::pushpop_extra_info.adoc[]
+include::cm_pop_popret_loads_pseudo_code.adoc[]
+include::cm_pop_pseudo_code.adoc[]
+
+include::Zcmp_footer.adoc[]
+
diff --git a/src/zc/cm_pop_popret_loads_pseudo_code.adoc b/src/zc/cm_pop_popret_loads_pseudo_code.adoc
new file mode 100644
index 0000000..af46b9d
--- /dev/null
+++ b/src/zc/cm_pop_popret_loads_pseudo_code.adoc
@@ -0,0 +1,25 @@
+
+Operation::
+
+The first section of pseudo-code may be executed multiple times before the instruction successfully completes.
+
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+if (XLEN==32) bytes=4; else bytes=8;
+
+addr=sp+stack_adj-bytes;
+for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1)  {
+  //if register i is in xreg_list
+  if (xreg_list[i]) {
+    switch(bytes) {
+      4:  asm("lw x[i], 0(addr)");
+      8:  asm("ld x[i], 0(addr)");
+    }
+    addr-=bytes;
+  }
+}
+--
+
+The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.
diff --git a/src/zc/cm_pop_pseudo_code.adoc b/src/zc/cm_pop_pseudo_code.adoc
new file mode 100644
index 0000000..0cd38a0
--- /dev/null
+++ b/src/zc/cm_pop_pseudo_code.adoc
@@ -0,0 +1,7 @@
+
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+sp+=stack_adj;
+--
diff --git a/src/zc/cm_popret.adoc b/src/zc/cm_popret.adoc
new file mode 100644
index 0000000..1150203
--- /dev/null
+++ b/src/zc/cm_popret.adoc
@@ -0,0 +1,49 @@
+<<<
+[#insns-cm_popret,reftext="Pop registers, deallocate stack frame, return."]
+=== cm.popret
+
+Synopsis::
+Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.
+
+Mnemonic::
+cm.popret _{reg_list}, stack_adj_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,             attr: ['C2'] },
+    { bits:  2, name: 'spimm\[5:4\]',  attr: [] },
+    { bits:  4, name: 'rlist',         attr: [] },
+    { bits:  5, name: 0x1e,            attr: [] },
+    { bits:  3, name: 0x5,             attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+
+  _rlist_ values 0 to 3 are reserved for a future EABI variant called _cm.popret.e_
+
+Assembly Syntax::
+
+[source,sail]
+--
+cm.popret {reg_list},  stack_adj
+cm.popret {xreg_list}, stack_adj
+--
+
+include::variable_def.adoc[]
+include::pushpop_vars.adoc[]
+
+<<<
+
+Description::
+This instruction pops (loads) the registers in _reg_list_ from stack memory,
+ adjusts the stack pointer by _stack_adj_ and then returns to _ra_.
+
+include::pushpop_extra_info.adoc[]
+include::cm_pop_popret_loads_pseudo_code.adoc[]
+include::cm_popret_pseudo_code.adoc[]
+
+include::Zcmp_footer.adoc[]
+
diff --git a/src/zc/cm_popret_pseudo_code.adoc b/src/zc/cm_popret_pseudo_code.adoc
new file mode 100644
index 0000000..ecf60f2
--- /dev/null
+++ b/src/zc/cm_popret_pseudo_code.adoc
@@ -0,0 +1,9 @@
+
+
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+sp+=stack_adj;
+asm("ret");
+--
diff --git a/src/zc/cm_popretz.adoc b/src/zc/cm_popretz.adoc
new file mode 100644
index 0000000..10ccf35
--- /dev/null
+++ b/src/zc/cm_popretz.adoc
@@ -0,0 +1,49 @@
+<<<
+[#insns-cm_popretz,reftext="Pop registers, deallocate stack frame, return zero."]
+=== cm.popretz
+
+Synopsis::
+Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.
+
+Mnemonic::
+cm.popretz _{reg_list}, stack_adj_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,             attr: ['C2'] },
+    { bits:  2, name: 'spimm\[5:4\]',  attr: [] },
+    { bits:  4, name: 'rlist',         attr: [] },
+    { bits:  5, name: 0x1c,            attr: [] },
+    { bits:  3, name: 0x5,             attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+
+  _rlist_ values 0 to 3 are reserved for a future EABI variant called _cm.popretz.e_
+
+
+Assembly Syntax::
+
+[source,sail]
+--
+cm.popretz {reg_list},  stack_adj
+cm.popretz {xreg_list}, stack_adj
+--
+
+include::pushpop_vars.adoc[]
+
+<<<
+
+Description::
+This instruction pops (loads) the registers in _reg_list_ from stack memory,
+ adjusts the stack pointer by _stack_adj_, moves zero into a0 and then returns to _ra_.
+
+include::pushpop_extra_info.adoc[]
+include::cm_pop_popret_loads_pseudo_code.adoc[]
+include::cm_popretz_pseudo_code.adoc[]
+
+include::Zcmp_footer.adoc[]
+
diff --git a/src/zc/cm_popretz_pseudo_code.adoc b/src/zc/cm_popretz_pseudo_code.adoc
new file mode 100644
index 0000000..6aac95c
--- /dev/null
+++ b/src/zc/cm_popretz_pseudo_code.adoc
@@ -0,0 +1,14 @@
+
+
+[NOTE]
+
+  The _li a0, 0_ *could* be executed more than once, but is included in the atomic section for convenience.
+
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+asm("li a0, 0");
+sp+=stack_adj;
+asm("ret");
+--
diff --git a/src/zc/cm_push.adoc b/src/zc/cm_push.adoc
new file mode 100644
index 0000000..77f1fde
--- /dev/null
+++ b/src/zc/cm_push.adoc
@@ -0,0 +1,48 @@
+<<<
+[#insns-cm_push,reftext="Create stack frame: push registers, allocate additional stack space."]
+=== cm.push
+
+Synopsis::
+Create stack frame: store ra and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space.
+
+Mnemonic::
+cm.push _{reg_list}, -stack_adj_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,             attr: ['C2'] },
+    { bits:  2, name: 'spimm\[5:4\]',  attr: [] },
+    { bits:  4, name: 'rlist',         attr: [] },
+    { bits:  5, name: 0x18,            attr: [] },
+    { bits:  3, name: 0x5,             attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+
+  _rlist_ values 0 to 3 are reserved for a future EABI variant called _cm.push.e_
+
+Assembly Syntax::
+
+[source,sail]
+--
+cm.push {reg_list},  -stack_adj
+cm.push {xreg_list}, -stack_adj
+--
+
+include::variable_def.adoc[]
+include::pushpop_vars.adoc[]
+
+<<<
+Description::
+This instruction pushes (stores) the registers in _reg_list_ to the memory below the stack pointer, 
+and then creates the stack frame by decrementing the stack pointer by _stack_adj_, 
+including any additional stack space requested by the value of _spimm_.
+
+include::pushpop_extra_info.adoc[]
+include::cm_push_stores_pseudo_code.adoc[]
+include::cm_push_pseudo_code.adoc[]
+
+include::Zcmp_footer.adoc[]
diff --git a/src/zc/cm_push_pseudo_code.adoc b/src/zc/cm_push_pseudo_code.adoc
new file mode 100644
index 0000000..8500f0e
--- /dev/null
+++ b/src/zc/cm_push_pseudo_code.adoc
@@ -0,0 +1,7 @@
+
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+sp-=stack_adj;
+--
diff --git a/src/zc/cm_push_stores_pseudo_code.adoc b/src/zc/cm_push_stores_pseudo_code.adoc
new file mode 100644
index 0000000..46771dd
--- /dev/null
+++ b/src/zc/cm_push_stores_pseudo_code.adoc
@@ -0,0 +1,25 @@
+
+Operation::
+
+The first section of pseudo-code may be executed multiple times before the instruction successfully completes.
+
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+if (XLEN==32) bytes=4; else bytes=8;
+
+addr=sp-bytes;
+for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1)  {
+  //if register i is in xreg_list
+  if (xreg_list[i]) {
+    switch(bytes) {
+      4:  asm("sw x[i], 0(addr)");
+      8:  asm("sd x[i], 0(addr)");
+    }
+    addr-=bytes;
+  }
+}
+--
+
+The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.
diff --git a/src/zc/cm_sb.adoc b/src/zc/cm_sb.adoc
new file mode 100644
index 0000000..265d039
--- /dev/null
+++ b/src/zc/cm_sb.adoc
@@ -0,0 +1,50 @@
+<<<
+[#insns-cm_sb,reftext="Store byte, 16-bit encoding"]
+=== cm.sb
+
+Synopsis::
+Store byte, 16-bit encoding
+
+Mnemonic::
+cm.sb _rs2'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rs2\'' },
+    { bits:  2, name: 'uimm[2:1]' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  2, name: 'uimm[0|3]' },
+    { bits:  1, name: 0x0 },
+    { bits:  3, name: 0x5, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+  If _uimm < 4_ the encoding is designated for custom use, as the functionality overlaps with <<insns-c_sb>>.
+
+include::cm_lbsb_imm_offset.adoc[]
+
+Description::
+This instruction stores the least significant byte of _rs2'_ to the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. 
+
+[NOTE]
+  _rs1'_ and _rs2'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-sb>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)
+--
+
+include::Zcmb_footer.adoc[]
diff --git a/src/zc/cm_sh.adoc b/src/zc/cm_sh.adoc
new file mode 100644
index 0000000..fb5e538
--- /dev/null
+++ b/src/zc/cm_sh.adoc
@@ -0,0 +1,51 @@
+<<<
+[#insns-cm_sh,reftext="Store halfword, 16-bit encoding"]
+=== cm.sh
+
+Synopsis::
+Store halfword, 16-bit encoding
+
+Mnemonic::
+cm.sh _rs2'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rs2\'' },
+    { bits:  2, name: 'uimm[2:1]' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  2, name: 'uimm[4:3]' },
+    { bits:  1, name: 0x1 },
+    { bits:  3, name: 0x5, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+[NOTE]
+  If _uimm < 4_ the encoding is designated for custom use, as the functionality overlaps with <<insns-c_sh>>.
+
+include::cm_lhsh_imm_offset.adoc[]
+
+Description::
+This instruction stores the least significant halfword of _rs2'_ to the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. 
+
+[NOTE]
+  _rs1'_ and _rs2'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-sh>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c)
+--
+
+include::Zcmb_footer.adoc[]
+
diff --git a/src/zc/example.bib b/src/zc/example.bib
new file mode 100644
index 0000000..dd4ca0b
--- /dev/null
+++ b/src/zc/example.bib
@@ -0,0 +1,40 @@
+@inproceedings{riscI-isca1981,
+  title = {{RISC I}: {A} Reduced Instruction Set {VLSI} Computer},
+  author = {David A. Patterson and Carlo H. S\'{e}quin},
+  booktitle = {ISCA},
+ location = {Minneapolis, Minnesota, USA},
+  pages = {443-458},
+  year = {1981}
+}
+
+@InProceedings{Katevenis:1983,
+ author = {Katevenis, Manolis G.H. and Sherburne,Jr., Robert W. and Patterson, David A. and S{\'e}quin, Carlo H.},
+ title = {The {RISC II} micro-architecture},
+  booktitle = {Proceedings VLSI 83 Conference},
+  year =      1983,
+  month =     {August}}
+
+@inproceedings{Ungar:1984,
+ author = {David Ungar and Ricki Blau and Peter Foley and Dain Samples
+                  and David Patterson},
+ title = {Architecture of {SOAR}: {Smalltalk} on a {RISC}},
+ booktitle = {ISCA},
+ address = {Ann Arbor, MI},
+ year = {1984},
+ pages = {188--197}
+} 
+
+@Article{spur-jsscc1989,
+  author =       {David D. Lee and Shing I. Kong and Mark D. Hill and
+                  George S. Taylor and David A. Hodges and Randy
+                  H. Katz and David A. Patterson},
+  title =        {A {VLSI} Chip Set for a Multiprocessor
+                  Workstation--{Part I}: An {RISC} Microprocessor with
+                  Coprocessor Interface and Support for Symbolic
+                  Processing},
+  journal =      {IEEE JSSC},
+  year =         1989,
+  volume =    24,
+  number =    6,
+  pages =     {1688--1698},
+  month =     {December}}
diff --git a/src/zc/jvt_csr.adoc b/src/zc/jvt_csr.adoc
new file mode 100644
index 0000000..9ad2367
--- /dev/null
+++ b/src/zc/jvt_csr.adoc
@@ -0,0 +1,65 @@
+<<<
+[#csrs-jvt,reftext="JVT CSR, table jump base vector and control register"]
+=== JVT CSR
+
+Synopsis::
+Table jump base vector and control register
+
+Address::
+0x0017
+
+Permissions::
+URW
+
+Format (RV32)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  6, name: 'mode',  attr: ['6'] },
+    { bits: 26, name: 'base[XLEN-1:6] (WARL)',  attr: ['XLEN-6'] },
+],config:{bits:32}}
+....
+
+Format (RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  6, name: 'mode',  attr: ['6'] },
+    { bits: 58, name: 'base[XLEN-1:6] (WARL)',  attr: ['XLEN-6'] },
+],config:{bits:64}}
+....
+
+Description::
+
+The _JVT_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).
+
+If <<Zcmt>> is implemented then _JVT_ must also be implemented, but can contain a read-only value. If _JVT_ is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary.
+
+_JVT.base_ is a virtual address, whenever virtual memory is enabled.
+
+The memory pointed to by _JVT.base_ is treated as instruction memory for the purpose of executing table jump instructions, implying execute access permission. 
+
+[#JVT-config-table]
+._JVT.mode_ definition
+[width="60%",options=header]
+|=============================================================================================
+| JVT.mode | Comment
+| 000000 | Jump table mode
+| others | *reserved for future standard use*
+|=============================================================================================
+
+_JVT.mode_ is a *WARL* field, so can only be programmed to modes which are implemented. Therefore the discovery mechanism is to 
+attempt to program different modes and read back the values to see which are available. Jump table mode _must_ be implemented.
+
+NOTE: in future the RISC-V Unified Discovery method will report the available modes.
+
+Architectural State::
+
+_JVT_ adds architectural state to the system software context (such as an OS process), therefore must be saved/restored on context switches. 
+
+State Enable::
+
+If the Smstateen extension is implemented, then bit 2 in _mstateen0_, _sstateen0_, and _hstateen0_ is implemented.  If bit 2 of a controlling _stateen0_ CSR is zero, then access to the _JVT_ CSR and execution of a _cm.jalt_ or _cm.jt_ instruction by a lower privilege level results in an Illegal Instruction trap (or, if appropriate, a Virtual Instruction trap).
+
+include::Zcmt_footer.adoc[]
+
diff --git a/src/zc/pushpop.adoc b/src/zc/pushpop.adoc
new file mode 100644
index 0000000..e4d61b8
--- /dev/null
+++ b/src/zc/pushpop.adoc
@@ -0,0 +1,349 @@
+<<<
+
+[#insns-pushpop,reftext="PUSH/POP Register Instructions"]
+== PUSH/POP register instructions
+
+These instructions are collectively referred to as PUSH/POP: 
+
+* <<#insns-cm_push>> 
+* <<#insns-cm_pop>> 
+* <<#insns-cm_popret>> 
+* <<#insns-cm_popretz>> 
+
+The term PUSH refers to _cm.push_.
+
+The term POP refers to _cm.pop_.
+
+The term POPRET refers to _cm.popret and cm.popretz_.
+
+Common details for these instructions are in this section.
+
+=== PUSH/POP functional overview
+
+PUSH, POP, POPRET are used to reduce the size of function prologues and epilogues.
+
+. The PUSH instruction
+** adjusts the stack pointer to create the stack frame
+** pushes (stores) the registers specified in the register list to the stack frame
+
+. The POP instruction
+** pops (loads) the registers in the register list from the stack frame
+** adjusts the stack pointer to destroy the stack frame
+
+. The POPRET instructions
+** pop (load) the registers in the register list from the stack frame
+** _cm.popretz_ also moves zero into _a0_ as the return value
+** adjust the stack pointer  to destroy the stack frame
+** execute a _ret_ instruction to return from the function
+
+<<<
+=== Example usage
+
+This example gives an illustration of the use of PUSH and POPRET.
+
+The function _processMarkers_ in the EMBench benchmark picojpeg in the following file on github: https://github.com/embench/embench-iot/blob/master/src/picojpeg/libpicojpeg.c[libpicojpeg.c]
+
+The prologue and epilogue compile with GCC10 to:
+
+[source,SAIL]
+----
+
+   0001098a <processMarkers>:
+   1098a:       711d                    addi    sp,sp,-96 ;#cm.push(1)
+   1098c:       c8ca                    sw      s2,80(sp) ;#cm.push(2)
+   1098e:       c6ce                    sw      s3,76(sp) ;#cm.push(3)
+   10990:       c4d2                    sw      s4,72(sp) ;#cm.push(4)
+   10992:       ce86                    sw      ra,92(sp) ;#cm.push(5)
+   10994:       cca2                    sw      s0,88(sp) ;#cm.push(6)
+   10996:       caa6                    sw      s1,84(sp) ;#cm.push(7)
+   10998:       c2d6                    sw      s5,68(sp) ;#cm.push(8)
+   1099a:       c0da                    sw      s6,64(sp) ;#cm.push(9)
+   1099c:       de5e                    sw      s7,60(sp) ;#cm.push(10)
+   1099e:       dc62                    sw      s8,56(sp) ;#cm.push(11)
+   109a0:       da66                    sw      s9,52(sp) ;#cm.push(12)
+   109a2:       d86a                    sw      s10,48(sp);#cm.push(13)
+   109a4:       d66e                    sw      s11,44(sp);#cm.push(14)
+...
+   109f4:       4501                    li      a0,0      ;#cm.popretz(1)
+   109f6:       40f6                    lw      ra,92(sp) ;#cm.popretz(2)
+   109f8:       4466                    lw      s0,88(sp) ;#cm.popretz(3)
+   109fa:       44d6                    lw      s1,84(sp) ;#cm.popretz(4)
+   109fc:       4946                    lw      s2,80(sp) ;#cm.popretz(5)
+   109fe:       49b6                    lw      s3,76(sp) ;#cm.popretz(6)
+   10a00:       4a26                    lw      s4,72(sp) ;#cm.popretz(7)
+   10a02:       4a96                    lw      s5,68(sp) ;#cm.popretz(8)
+   10a04:       4b06                    lw      s6,64(sp) ;#cm.popretz(9)
+   10a06:       5bf2                    lw      s7,60(sp) ;#cm.popretz(10)
+   10a08:       5c62                    lw      s8,56(sp) ;#cm.popretz(11)
+   10a0a:       5cd2                    lw      s9,52(sp) ;#cm.popretz(12)
+   10a0c:       5d42                    lw      s10,48(sp);#cm.popretz(13)
+   10a0e:       5db2                    lw      s11,44(sp);#cm.popretz(14)
+   10a10:       6125                    addi    sp,sp,96  ;#cm.popretz(15)
+   10a12:       8082                    ret               ;#cm.popretz(16)
+----
+
+<<<
+
+with the GCC option _-msave-restore_ the output is the following:
+
+[source,SAIL]
+----
+0001080e <processMarkers>:
+   1080e:       73a012ef                jal     t0,11f48 <__riscv_save_12>
+   10812:       1101                    addi    sp,sp,-32
+...
+   10862:       4501                    li      a0,0
+   10864:       6105                    addi    sp,sp,32
+   10866:       71e0106f                j       11f84 <__riscv_restore_12>
+----
+
+with PUSH/POPRET this reduces to
+
+[source,SAIL]
+----
+0001080e <processMarkers>:
+   1080e:       b8fa                    cm.push    {ra,s0-s11},-96
+...
+   10866:       bcfa                    cm.popretz {ra,s0-s11}, 96
+----
+
+The prologue / epilogue reduce from 60-bytes in the original code, to 14-bytes with _-msave-restore_, 
+and to 4-bytes with PUSH and POPRET. 
+As well as reducing the code-size PUSH and POPRET eliminate the branches from 
+calling the millicode _save/restore_ routines and so may also perform better. 
+  
+[NOTE]
+
+  The calls to _<riscv_save_0>/<riscv_restore_0>_ become 64-bit when the target functions are out of the ±1MB range, increasing the prologue/epilogue size to 22-bytes.
+
+[NOTE]
+
+  POP is typically used in tail-calling sequences where _ret_ is not used to return to _ra_ after destroying the stack frame.
+
+[#pushpop-areg-list]
+
+==== Stack pointer adjustment handling
+
+The instructions all automatically adjust the stack pointer by enough to cover the memory required for the registers being saved or restored. 
+Additionally the _spimm_ field in the encoding allows the stack pointer to be adjusted in additional increments of 16-bytes. There is only a small restricted
+range available in the encoding; if the range is insufficient then a separate _c.addi16sp_ can be used to increase the range.
+
+==== Register list handling
+
+There is no support for the _{ra, s0-s10}_ register list without also adding _s11_. Therefore the _{ra, s0-s11}_ register list must be used in this case.
+
+[#pushpop-idempotent-memory]
+=== PUSH/POP Fault handling
+
+Correct execution requires that _sp_ refers to idempotent memory (also see <<pushpop_non-idem-mem>>), because the core must be able to 
+handle traps detected during the sequence. 
+The entire PUSH/POP sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.
+
+If a trap occurs during the sequence then _xEPC_ is updated with the PC of the instruction, _xTVAL_ (if not read-only-zero) updated with the bad address if it was an access fault and _xCAUSE_ updated with the type of trap.
+
+NOTE: It is implementation defined whether interrupts can also be taken during the sequence execution.
+
+[#pushpop-software-view]
+=== Software view of execution
+
+==== Software view of the PUSH sequence
+
+From a software perspective the PUSH sequence appears as:
+
+* A sequence of stores writing the bytes required by the pseudo-code
+** The bytes may be written in any order.
+** The bytes may be grouped into larger accesses.
+** Any of the bytes may be written multiple times.
+* A stack pointer adjustment
+
+NOTE: If an implementation allows interrupts during the sequence, and the interrupt handler uses _sp_ to allocate stack memory, then any stores which were executed before the interrupt may be overwritten by the handler. This is safe because the memory is idempotent and the stores will be re-executed when execution resumes.
+
+The stack pointer adjustment must only be committed only when it is certain that the entire PUSH instruction will commit.
+
+Stores may also return imprecise faults from the bus. 
+It is platform defined whether the core implementation waits for the bus responses before continuing to the final stage of the sequence, 
+or handles errors responses after completing the PUSH instruction.
+
+<<<
+
+For example:
+
+[source,sail]
+--
+cm.push  {ra, s0-s5}, -64
+--
+
+Appears to software as:
+
+[source,sail]
+--
+# any bytes from sp-1 to sp-28 may be written multiple times before 
+# the instruction completes therefore these updates may be visible in 
+# the interrupt/exception handler below the stack pointer
+sw  s5, -4(sp)   
+sw  s4, -8(sp)   
+sw  s3,-12(sp)   
+sw  s2,-16(sp)  
+sw  s1,-20(sp)   
+sw  s0,-24(sp)   
+sw  ra,-28(sp)   
+
+# this must only execute once, and will only execute after all stores
+# completed without any precise faults, therefore this update is only 
+# visible in the interrupt/exception handler if cm.push has completed
+addi sp, sp, -64
+--
+
+==== Software view of the POP/POPRET sequence
+
+From a software perspective the POP/POPRET sequence appears as:
+
+* A sequence of loads reading the bytes required by the pseudo-code.
+** The bytes may be loaded in any order.
+** The bytes may be grouped into larger accesses.
+** Any of the bytes may be loaded multiple times.
+* A stack pointer adjustment
+* An optional `li a0, 0`
+* An optional `ret`
+
+If a trap occurs during the sequence, then any loads which were executed before the trap may update architectural state. 
+The loads will be re-executed once the trap handler completes, so the values will be overwritten. 
+Therefore it is permitted for an implementation to update some of the destination registers before taking a fault.
+
+The optional `li a0, 0`, stack pointer adjustment and optional `ret` must only be committed only when it is certain that the entire POP/POPRET instruction will commit.
+
+For POPRET once the stack pointer adjustment has been committed the `ret` must execute.
+
+<<<
+For example:
+
+[source,sail]
+--
+cm.popretz {ra, s0-s3}, 32;
+--
+
+Appears to software as:
+
+[source,sail]
+--
+# any or all of these load instructions may execute multiple times
+# therefore these updates may be visible in the interrupt/exception handler
+lw   s3, 28(sp)
+lw   s2, 24(sp)
+lw   s1, 20(sp)
+lw   s0, 16(sp)
+lw   ra, 12(sp)
+
+# these must only execute once, will only execute after all loads 
+# complete successfully all instructions must execute atomically
+# therefore these updates are not visible in the interrupt/exception handler
+li a0, 0
+addi sp, sp, 32
+ret
+--
+
+[[pushpop_non-idem-mem]]
+=== Non-idempotent memory handling
+
+An implementation may have a requirement to issue a PUSH/POP instruction to non-idempotent memory. 
+
+If the core implementation does not support PUSH/POP to non-idempotent memories, the core may use an idempotency PMA to detect it and take a 
+load (POP/POPRET) or store (PUSH) access fault exception in order to avoid unpredictable results.
+
+Software should only use these instructions on non-idempotent memory regions when software can tolerate the required memory accesses
+being issued repeatedly in the case that they cause exceptions.
+
+<<<
+
+=== Example RV32I PUSH/POP sequences
+
+The examples are included show the load/store series expansion and the stack adjustment. 
+Examples of _cm.popret_ and _cm.popretz_ are not included, as the difference in the expanded sequence from _cm.pop_ is trivial in all cases.
+
+==== cm.push  {ra, s0-s2}, -64
+
+Encoding: _rlist_=7, _spimm_=3
+
+expands to:
+
+[source,sail]
+--
+sw  s2,  -4(sp);
+sw  s1,  -8(sp);
+sw  s0, -12(sp);
+sw  ra, -16(sp);
+addi sp, sp, -64;
+--
+
+==== cm.push {ra, s0-s11}, -112
+
+Encoding: _rlist_=15, _spimm_=3
+
+expands to:
+
+[source,sail]
+--
+sw  s11,  -4(sp);
+sw  s10,  -8(sp);
+sw  s9,  -12(sp);
+sw  s8,  -16(sp);
+sw  s7,  -20(sp);
+sw  s6,  -24(sp);
+sw  s5,  -28(sp);
+sw  s4,  -32(sp);
+sw  s3,  -36(sp);
+sw  s2,  -40(sp);
+sw  s1,  -44(sp);
+sw  s0,  -48(sp);
+sw  ra,  -52(sp);
+addi sp, sp, -112;
+--
+
+<<<
+
+==== cm.pop   {ra}, 16
+
+Encoding: _rlist_=4, _spimm_=0
+
+expands to:
+
+[source,sail]
+--
+lw   ra, 12(sp);
+addi sp, sp, 16;
+--
+
+==== cm.pop {ra, s0-s3}, 48
+
+Encoding: _rlist_=8, _spimm_=1
+
+expands to:
+
+[source,sail]
+--
+lw   s3, 44(sp);
+lw   s2, 40(sp);
+lw   s1, 36(sp);
+lw   s0, 32(sp);
+lw   ra, 28(sp);
+addi sp, sp, 48;
+--
+
+==== cm.pop {ra, s0-s4}, 64
+
+Encoding: _rlist_=9, _spimm_=2
+
+expands to: 
+
+[source,sail]
+--
+lw   s4, 60(sp);
+lw   s3, 56(sp);
+lw   s2, 52(sp);
+lw   s1, 48(sp);
+lw   s0, 44(sp);
+lw   ra, 40(sp);
+addi sp, sp, 64;
+--
+
+include::Zcmp_footer.adoc[]
diff --git a/src/zc/pushpop_extra_info.adoc b/src/zc/pushpop_extra_info.adoc
new file mode 100644
index 0000000..52bf69c
--- /dev/null
+++ b/src/zc/pushpop_extra_info.adoc
@@ -0,0 +1,22 @@
+
+[NOTE]
+
+  All ABI register mappings are for the UABI. An EABI version is planned once the EABI is frozen.
+
+For further information see <<insns-pushpop>>.
+
+Stack Adjustment Calculation::
+
+_stack_adj_base_ is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list. 
+
+_spimm_ is the number of additional 16-byte address increments allocated for the stack frame.
+
+The total stack adjustment represents the total size of the stack frame, which is _stack_adj_base_ added to _spimm_ scaled by 16, 
+as defined above.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+No direct equivalent encoding exists
+
diff --git a/src/zc/pushpop_vars.adoc b/src/zc/pushpop_vars.adoc
new file mode 100644
index 0000000..ce25524
--- /dev/null
+++ b/src/zc/pushpop_vars.adoc
@@ -0,0 +1,91 @@
+
+[source,sail]
+--
+RV32E:
+
+switch (rlist){
+  case  4: {reg_list="ra";         xreg_list="x1";}
+  case  5: {reg_list="ra, s0";     xreg_list="x1, x8";}
+  case  6: {reg_list="ra, s0-s1";  xreg_list="x1, x8-x9";}
+  default: reserved();
+}
+stack_adj      = stack_adj_base + spimm[5:4] * 16;
+--
+
+[source,sail]
+--
+RV32I, RV64:
+
+switch (rlist){
+  case  4: {reg_list="ra";         xreg_list="x1";}
+  case  5: {reg_list="ra, s0";     xreg_list="x1, x8";}
+  case  6: {reg_list="ra, s0-s1";  xreg_list="x1, x8-x9";}
+  case  7: {reg_list="ra, s0-s2";  xreg_list="x1, x8-x9, x18";}
+  case  8: {reg_list="ra, s0-s3";  xreg_list="x1, x8-x9, x18-x19";}
+  case  9: {reg_list="ra, s0-s4";  xreg_list="x1, x8-x9, x18-x20";}
+  case 10: {reg_list="ra, s0-s5";  xreg_list="x1, x8-x9, x18-x21";}
+  case 11: {reg_list="ra, s0-s6";  xreg_list="x1, x8-x9, x18-x22";}
+  case 12: {reg_list="ra, s0-s7";  xreg_list="x1, x8-x9, x18-x23";}
+  case 13: {reg_list="ra, s0-s8";  xreg_list="x1, x8-x9, x18-x24";}
+  case 14: {reg_list="ra, s0-s9";  xreg_list="x1, x8-x9, x18-x25";}
+  //note - to include s10, s11 must also be included
+  case 15: {reg_list="ra, s0-s11"; xreg_list="x1, x8-x9, x18-x27";}
+  default: reserved();
+}
+stack_adj      = stack_adj_base + spimm[5:4] * 16;
+--
+
+[source,sail]
+--
+RV32E:
+
+stack_adj_base = 16;
+Valid values:
+stack_adj      = [16|32|48|64];
+--
+
+[source,sail]
+--
+RV32I:
+
+switch (rlist) {
+  case  4.. 7: stack_adj_base = 16;
+  case  8..11: stack_adj_base = 32;
+  case 12..14: stack_adj_base = 48;
+  case     15: stack_adj_base = 64;
+}
+
+Valid values:
+switch (rlist) {
+  case  4.. 7: stack_adj = [16|32|48| 64];
+  case  8..11: stack_adj = [32|48|64| 80];
+  case 12..14: stack_adj = [48|64|80| 96];
+  case     15: stack_adj = [64|80|96|112];
+}
+--
+
+[source,sail]
+--
+RV64:
+
+switch (rlist) {
+  case  4.. 5: stack_adj_base =  16;
+  case  6.. 7: stack_adj_base =  32;
+  case  8.. 9: stack_adj_base =  48;
+  case 10..11: stack_adj_base =  64;
+  case 12..13: stack_adj_base =  80;
+  case     14: stack_adj_base =  96;
+  case     15: stack_adj_base = 112;
+}
+
+Valid values:
+switch (rlist) {
+  case  4.. 5: stack_adj = [ 16| 32| 48| 64];
+  case  6.. 7: stack_adj = [ 32| 48| 64| 80];
+  case  8.. 9: stack_adj = [ 48| 64| 80| 96];
+  case 10..11: stack_adj = [ 64| 80| 96|112];
+  case 12..13: stack_adj = [ 80| 96|112|128];
+  case     14: stack_adj = [ 96|112|128|144];
+  case     15: stack_adj = [112|128|144|160];
+}
+--
diff --git a/src/zc/readme.md b/src/zc/readme.md
new file mode 100644
index 0000000..8a333e7
--- /dev/null
+++ b/src/zc/readme.md
@@ -0,0 +1,15 @@
+This directory has the latest draft specification for the Zc extensions, without the PDF build.
+
+To see the latest built version go to:
+
+https://github.com/riscv/riscv-code-size-reduction/tags
+
+The benchmarking results for all Zc extensions are here:
+
+https://docs.google.com/spreadsheets/d/1bFMyGkuuulBXuIaMsjBINoCWoLwObr1l9h5TAWN8s7k/edit#gid=21966619
+
+There are many changes since v0.50.1, which has been used for toolchain, spike, qemu and the CV32E41P implementation.
+
+This shows how the specification has changed from v0.50.1 to the current version:
+
+https://github.com/riscv/riscv-code-size-reduction/blob/master/Zc-specification/changes_since_v0.50.adoc
diff --git a/src/zc/tablejump.adoc b/src/zc/tablejump.adoc
new file mode 100644
index 0000000..fefa8fc
--- /dev/null
+++ b/src/zc/tablejump.adoc
@@ -0,0 +1,49 @@
+<<<
+
+[#insns-tablejump,reftext="Table Jump Overview"]
+== Table Jump Overview
+
+_cm.jt_ (<<#insns-cm_jt>>) and _cm.jalt_ (<<#insns-cm_jalt>>) are referred to as table jump.
+
+Table jump uses a 256-entry XLEN wide table in instruction memory to contain function addresses.
+The table must be a minimum of 64-byte aligned.
+
+Table entries follow the current data endianness. This is different from normal instruction fetch which is always little-endian.
+
+_cm.jt_ and _cm.jalt_ encodings index the table, giving access to functions within the full XLEN wide address space.
+
+This is used as a form of dictionary compression to reduce the code size of _jal_ / _auipc+jalr_ / _jr_ / _auipc+jr_ instructions.
+
+Table jump allows the linker to replace the following instruction sequences with a _cm.jt_ or _cm.jalt_ encoding, and an entry in the table:
+
+* 32-bit _j_ calls 
+* 32-bit _jal_ ra calls 
+* 64-bit _auipc+jr_ calls to fixed locations 
+* 64-bit _auipc+jalr ra_ calls to fixed locations 
+** The _auipc+jr/jalr_ sequence is used because the offset from the PC is out of the ±1MB range.
+
+If a return address stack is implemented, then as _cm.jalt_ is equivalent to _jal ra_, it pushes to the stack.
+
+=== JVT
+
+The base of the table is in the JVT CSR (see <<csrs-jvt>>), each table entry is XLEN bits.
+
+If the same function is called with and without linking then it must have two entries in the table. 
+This is typically caused by the same function being called with and without tail calling.
+
+[#tablejump-fault-handling]
+=== Table Jump Fault handling
+
+For a table jump instruction, the table entry that the instruction selects is considered an extension of the instruction itself.
+Hence, the execution of a table jump instruction involves two instruction fetches, the first to read the instruction (_cm.jt_/_cm.jalt_) 
+and the second to read from the jump vector table (JVT). Both instruction fetches are _implicit_ reads, and both require
+execute permission; read permission is irrelevant. It is recommended that the second fetch be ignored for hardware triggers and breakpoints.
+
+Memory writes to the jump vector table require an instruction barrier (_fence.i_) to guarantee that they are visible to the instruction fetch.
+
+Multiple contexts may have different jump vector tables. JVT may be switched between them without an instruction barrier 
+if the tables have not been updated in memory since the last _fence.i_.
+
+If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction,  xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.
+
+include::Zcmt_footer.adoc[]
diff --git a/src/zc/variable_def.adoc b/src/zc/variable_def.adoc
new file mode 100644
index 0000000..a660cac
--- /dev/null
+++ b/src/zc/variable_def.adoc
@@ -0,0 +1 @@
+The variables used in the assembly syntax are defined below.