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+<<<
+[#insns-c_not,reftext="Bitwise not, 16-bit encoding"]
+=== c.not
+
+Synopsis::
+Bitwise not, 16-bit encoding
+
+Mnemonic::
+c.not _rd'/rs1'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x1, attr: ['C1'] },
+    { bits:  3, name: 0x5, attr: ['C.NOT'] },
+    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
+    { bits:  3, name: 0x7 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Description::
+This instruction takes the one's complement of _rd'/rs1'_ and writes the result to the same register.
+
+[NOTE]
+  _rd'/rs1'_ is from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+[source,sail]
+--
+xori rd'/rs1', rd'/rs1', -1
+--
+
+[NOTE]
+
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.
+
+Operation::
+[source,sail]
+--
+X(rsdc) = X(rsdc) XOR -1;
+--
+
+include::Zcb_footer.adoc[]
+