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+<<<
+[#insns-c_sh,reftext="Store halfword, 16-bit encoding"]
+=== c.sh
+
+Synopsis::
+Store halfword, 16-bit encoding
+
+Mnemonic::
+c.sh _rs2'_, _uimm_(_rs1'_)
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x0, attr: ['C0'] },
+    { bits:  3, name: 'rs2\'' },
+    { bits:  1, name: 'uimm[1]' },
+    { bits:  1, name: '0' },
+    { bits:  3, name: 'rs1\'' },
+    { bits:  3, name: 0x3 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+include::c_lhsh_imm_offset.adoc[]
+
+Description::
+This instruction stores the least significant halfword of _rs2'_ to the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. 
+
+[NOTE]
+  _rs1'_ and _rs2'_ are from the standard 8-register set x8-x15.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+<<insns-sh>>
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+
+mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c)
+--
+
+include::Zcb_footer.adoc[]
+