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+<<<
+[#insns-cm_mva01s,reftext="Move two s0-s7 registers into a0-a1"]
+=== cm.mva01s
+
+Synopsis::
+Move two s0-s7 registers into a0-a1
+
+Mnemonic::
+cm.mva01s _r1s'_, _r2s'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x2,      attr: ['C2'] },
+    { bits:  3, name: 'r2s\'',  attr: [] },
+    { bits:  2, name: 0x3,      attr: [] },
+    { bits:  3, name: 'r1s\'',  attr: [] },
+    { bits:  3, name: 0x3,      attr: [] },
+    { bits:  3, name: 0x5,      attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Assembly Syntax::
+
+[source,sail]
+--
+cm.mva01s r1s', r2s'
+--
+
+Description::
+This instruction moves _r1s'_ into _a0_ and _r2s'_ into _a1_. 
+The execution is atomic, so it is not possible to observe state where only one of _a0_ or _a1_ have been updated.
+
+The encoding uses _sreg_ number specifiers instead of _xreg_ number specifiers to save encoding space. 
+The mapping between them is specified in the pseudo-code below.
+
+[NOTE]
+
+  The _s_ register mapping is taken from the UABI, and may not match the currently unratified EABI. _cm.mva01s.e_ may be included in the future.
+
+Prerequisites::
+None
+
+32-bit equivalent::
+No direct equivalent encoding exists.
+
+Operation::
+[source,sail]
+--
+//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
+if (RV32E && (r1sc>1 || r2sc>1)) {
+  reserved();
+}
+xreg1 = {r1sc[2:1]>0,r1sc[2:1]==0,r1sc[2:0]};
+xreg2 = {r2sc[2:1]>0,r2sc[2:1]==0,r2sc[2:0]};
+X[10] = X[xreg1];
+X[11] = X[xreg2];
+--
+
+include::Zcmp_footer.adoc[]
+