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<<<
[#insns-cm_lhu,reftext="Load unsigned halfword, 16-bit encoding"]
=== cm.lhu
Synopsis::
Load unsigned halfword, 16-bit encoding
Mnemonic::
cm.lhu _rd'_, _uimm_(_rs1'_)
Encoding (RV32, RV64)::
[wavedrom, , svg]
....
{reg:[
{ bits: 2, name: 0x2, attr: ['C2'] },
{ bits: 3, name: 'rd\'' },
{ bits: 2, name: 'uimm[2:1]' },
{ bits: 3, name: 'rs1\'' },
{ bits: 2, name: 'uimm[4:3]' },
{ bits: 1, name: 0x1 },
{ bits: 3, name: 0x1, attr: ['FUNCT3'] },
],config:{bits:16}}
....
[NOTE]
If _uimm < 4_ the encoding is designated for custom use, as the functionality overlaps with <<insns-c_lhu>>.
include::cm_lhsh_imm_offset.adoc[]
Description::
This instruction loads a halfword from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting halfword is zero extended to XLEN bits and is written to _rd'_.
[NOTE]
_rd'_ and _rs1'_ are from the standard 8-register set x8-x15.
Prerequisites::
None
32-bit equivalent::
<<insns-lhu>>
Operation::
[source,sail]
--
//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);
--
include::Zcmb_footer.adoc[]
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