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Signed-off-by: liangzhen <zhen.liang@spacemit.com>
Change-Id: Ida1490338d204541c5c7f143aec3b8d79d83d7f4
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Signed-off-by: liangzhen <zhen.liang@spacemit.com>
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Also make the semi-hosting test program return 10. That's more fragile
than returning 0, so makes for a better test.
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`cease` is not a standard RISC-V extension, but is (was?) implemented in
Rocket, and also exists in some SiFive cores. It's useful to test
OpenOCD behavior when a hart becomes unavailable.
See also https://github.com/chipsalliance/rocket-chip/issues/1868
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Also change the test itself to require less RAM than it did previously.
(It had required more than 32KB.)
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It would fail intermittently. We can't guarantee all harts resume
simultaneously. When we let multiple harts run to a breakpoint at the
end of the same loop, one is likely to get there first, and the second
won't make it.
To avoid this problem, run for a short amount of time instead of to a
breakpoint.
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* Specify trigger type=2 in trigger.S
Previous tests implicitly assume triggers only support type=2. However,
a trigger may support multiple types, i.e., type=15. This commit
explicitly specifies type=2 in trigger.S to support type 15.
* Update debug/programs/trigger.S
Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
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In the original test, confirm that stdout data ends up in the OpenOCD
log.
In the new test, with `arm semihosting_fileio` enabled, confirm that
stdout data ends up in gdb's CLI.
This test requires https://github.com/riscv/riscv-openocd/pull/699.
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* Add EbreakTest.
Confirm correct behavior when somebody bakes an ebreak instruction into
their code.
* Forgot to commit ebreak.c
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They used to set U, A, D, in intermediate page table entries which is no
longer allowed.
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* WIP
* WIP
* Vector test seems to work well with spike.
* Check a0 in case the program didn't work right.
* Return not applicable if compile doesn't support V
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* Add a basic semihosting test.
* Need to configure semihosting on each target.
* WIP
* Parse "cannot insert breakpoint" message.
Also use sys.exit instead of exit, per new pylint's suggestion.
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* Improve address translation tests.
Check that the mode we're testing is supported by hardware before
running the test.
Test with high address bits set, which catches a bug in OpenOCD.
* Turn off PMP for address translation test.
Otherwise it doesn't pass on HiFive Unleashed.
* Run TranslateTest on random hart.
Once https://github.com/riscv/riscv-openocd/pull/459 merges that will work.
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This way if you end up reading a value that you suspect might be coming
from another hart/register, you can clearly see where it came from.
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* WIP
* Smoke test virtual address support.
Tests sv32, sv39, and sv48. Only explicitly tests 4K pages, but uses as
large as possible pages to 1:1 map the rest of RAM so those sizes do get
minimal coverage as well.
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Passes on spike and Arty. Won't merge until
https://github.com/riscv/riscv-openocd/pull/364 merges.
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This test confirms that in SMP configurations OpenOCD halts the harts
near-simulatenously. (It'll also check for resume, but that's not
implemented yet so commented out for now.)
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Only TriggerDmode still fails.
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Not all tests pass when run out of flash yet, but it's getting a lot
closer. The ones still failing on HiFive1-flash are: DebugSymbols,
Hwbp2, InstantHaltTest, TriggerDmode, TriggerLoadAddressInstant, and
TriggerStoreAddressInstant.
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Also tiny cleanups, making pylint happy.
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Add interrupts to MulticoreRunHaltStepiTest.
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Fixes #77.
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Just to hammer on anything at once, and hopefully catch weird
interactions if they exist.
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When compiling, define the number of harts. This means we only need to
allocate a lot of stack if there are a lot of harts.
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Targets now contain an array of harts. When running a regular test, one
hart is selected to run the test on while the remaining harts are parked
in a safe infinite loop.
There's currently only one test that tests multicore behavior, but there
could be more.
The infrastructure should be able to support heterogeneous multicore,
but I don't have a target like that to test with.
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Then for targets that can't handle this because they don't implement
hmode, add a target setting that allows that to be specified.
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This shouldn't affect triggers set by the debugger, because running code
can't change those. When it does affect them, it breaks Hwbp1 which sets
the breakpoint before running the program.
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At least in the test programs. There are other places where this causes
trouble as well.
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When connecting to gdb, select a random thread and use that for the
current test.
Also replace infinite_loop with something that will later allow
smoketesting of more than one thread.
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The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000.
Also a minor change to log file naming so that 'make all' works again.
I'll fix this better later.
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Spike appears to have a problem geterating DTS at 0x80000000.
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(actually it just gets an exception anyway).
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