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| author | Tim Newsome <tim@sifive.com> | 2022-12-01 10:30:33 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-01 10:30:33 -0800 |
| commit | 6a4225fae83a1ad9bf9687c13f1046baa401269e (patch) | |
| tree | d7dee754d1067ba3fbe856ea3c7434659a7e18fb /debug/programs | |
| parent | 068241464ee28131a811f70bd2a78e299e60af91 (diff) | |
| download | riscv-tests-6a4225fae83a1ad9bf9687c13f1046baa401269e.zip riscv-tests-6a4225fae83a1ad9bf9687c13f1046baa401269e.tar.gz riscv-tests-6a4225fae83a1ad9bf9687c13f1046baa401269e.tar.bz2 | |
debug: Park unused harts with a cease instruction. (#434)
`cease` is not a standard RISC-V extension, but is (was?) implemented in
Rocket, and also exists in some SiFive cores. It's useful to test
OpenOCD behavior when a hart becomes unavailable.
See also https://github.com/chipsalliance/rocket-chip/issues/1868
Diffstat (limited to 'debug/programs')
| -rwxr-xr-x | debug/programs/entry.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 091efa4..09cad53 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -204,6 +204,18 @@ trap_entry: loop_forever: j loop_forever + .align 2 +precease: + // Loop a while so that OpenOCD might have confirmed the resume before the + // hart becomes unavailable. + li t1, 100000 +1: + addi t1, t1, -1 + bnez t1, 1b +cease: + .word 0x30500073 // cease + j loop_forever + // Fill the stack with data so we can see if it was overrun. .section .data .align 4 |