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| author | Tim Newsome <tim@sifive.com> | 2017-08-07 12:51:42 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-08-28 12:16:39 -0700 |
| commit | 3a44725d27f6b2c77f0ca912d792b6856fde6a17 (patch) | |
| tree | e89d52105aa01d59e7d4588ef157d477f0a4335d /debug/programs | |
| parent | ab6c2ccaec192684cf4649d5d69bd105d738d1c7 (diff) | |
| download | riscv-tests-3a44725d27f6b2c77f0ca912d792b6856fde6a17.zip riscv-tests-3a44725d27f6b2c77f0ca912d792b6856fde6a17.tar.gz riscv-tests-3a44725d27f6b2c77f0ca912d792b6856fde6a17.tar.bz2 | |
Make the debug tests aware of multicore.
Targets now contain an array of harts. When running a regular test, one
hart is selected to run the test on while the remaining harts are parked
in a safe infinite loop.
There's currently only one test that tests multicore behavior, but there
could be more.
The infrastructure should be able to support heterogeneous multicore,
but I don't have a target like that to test with.
Diffstat (limited to 'debug/programs')
| -rwxr-xr-x | debug/programs/entry.S | 7 | ||||
| -rw-r--r-- | debug/programs/start.S | 12 |
2 files changed, 7 insertions, 12 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index ff8ae30..c3be611 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -157,9 +157,16 @@ trap_entry: addi sp, sp, 32*REGBYTES mret +loop_forever: + j loop_forever + // Fill the stack with data so we can see if it was overrun. .align 4 stack_bottom: .fill STACK_SIZE/4, 4, 0x22446688 stack_top: + // Prevent stack_top from being identical to next symbol, which may cause gdb + // to report we're halted at stack_top which happens to be the same address + // as main. + .word 0 #endif diff --git a/debug/programs/start.S b/debug/programs/start.S deleted file mode 100644 index 76c37bb..0000000 --- a/debug/programs/start.S +++ /dev/null @@ -1,12 +0,0 @@ - .global _start - -_start: - la sp, stack_end - jal main -done: - j done - - .data -stack: - .fill 4096, 1, 0 -stack_end: |