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author | Tim Newsome <tim@sifive.com> | 2019-04-04 11:40:08 -0700 |
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committer | GitHub <noreply@github.com> | 2019-04-04 11:40:08 -0700 |
commit | 74aecdcce266d2d7f73df415cb83b6e7816e0dc5 (patch) | |
tree | d712af2e9f68d10fafbcaf64176f5aae7411e622 /debug/programs | |
parent | 91b6f8fdda47323fd6af16320b6560d325ac6317 (diff) | |
download | riscv-tests-74aecdcce266d2d7f73df415cb83b6e7816e0dc5.zip riscv-tests-74aecdcce266d2d7f73df415cb83b6e7816e0dc5.tar.gz riscv-tests-74aecdcce266d2d7f73df415cb83b6e7816e0dc5.tar.bz2 |
Test simultaneous resume using hasel. (#186)
Passes on spike and Arty. Won't merge until
https://github.com/riscv/riscv-openocd/pull/364 merges.
Diffstat (limited to 'debug/programs')
-rw-r--r-- | debug/programs/run_halt_timing.S | 18 | ||||
-rw-r--r-- | debug/programs/run_halt_timing.c | 17 |
2 files changed, 18 insertions, 17 deletions
diff --git a/debug/programs/run_halt_timing.S b/debug/programs/run_halt_timing.S new file mode 100644 index 0000000..ce4000a --- /dev/null +++ b/debug/programs/run_halt_timing.S @@ -0,0 +1,18 @@ +#if XLEN == 64 +# define LREG ld +# define SREG sd +# define REGBYTES 8 +#else +# define LREG lw +# define SREG sw +# define REGBYTES 4 +#endif + + .global main +main: + li s0, 0 + li s1, 0x0200bff8 +loop: + addi s0, s0, 1 + LREG s2, 0(s1) + j loop diff --git a/debug/programs/run_halt_timing.c b/debug/programs/run_halt_timing.c deleted file mode 100644 index 1c9a8ba..0000000 --- a/debug/programs/run_halt_timing.c +++ /dev/null @@ -1,17 +0,0 @@ -#include <stdio.h> -#include <string.h> -#include <stdint.h> -#include <stdlib.h> - -#include "init.h" - -int main() -{ - int counter = 0; - volatile uint64_t mtime_value; - - while (1) { - counter = counter + 1; - mtime_value = MTIME; - } -} |