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path: root/riscv/decode.h
AgeCommit message (Expand)AuthorFilesLines
2020-06-04rvv: fix compilation warningChih-Min Chao1-6/+6
2020-05-28rvv: use zvqmac to enable vector qmacChih-Min Chao1-0/+1
2020-05-28rvv: apply new overlapping and align macroChih-Min Chao1-53/+46
2020-05-28rvv: add e8 type for narrow/widen conversionChih-Min Chao1-5/+24
2020-05-28rvv: add new explicit eew load/store instructionsChih-Min Chao1-108/+122
2020-05-28rvv: add amo instructionsChih-Min Chao1-0/+43
2020-05-28rvv: add new singed/unsiged extension instructionsChih-Min Chao1-0/+40
2020-05-28rvv: wrap align and overlap checking macroChih-Min Chao1-4/+31
2020-05-28rvv: remove vmlenChih-Min Chao1-11/+10
2020-05-28rvv: handle inactive and NaN case for vfredsumChih-Min Chao1-2/+51
2020-05-04rvv: fp16: support vfwxxx.[wv][vf] instructionsChih-Min Chao1-19/+42
2020-05-04rvv: fp16: support conversion instrucitonsChih-Min Chao1-0/+27
2020-05-04rvv: fp16: support reduction instructionsChih-Min Chao1-9/+38
2020-05-04rvv: fp16: support comparison instructionsChih-Min Chao1-2/+9
2020-05-04rvv: fp16: support .vf instructionsChih-Min Chao1-3/+9
2020-05-04rvv: fp16: support .vv instructionsChih-Min Chao1-3/+11
2020-05-04rvv: remove unused WIDE_END loop macroChih-Min Chao1-9/+4
2020-05-04fp16: add helper macroChih-Min Chao1-0/+8
2020-04-28rvv: commitlog: fix vmsgtu.vi and vmsleu.vi dst informationChih-Min Chao1-4/+7
2020-04-24rvv: commitlog: fix dst information for int comparisonChih-Min Chao1-20/+40
2020-04-24rvv: leave only SEW-bit segment storeChih-Min Chao1-5/+7
2020-04-24rvv: leave only SEW-bit segment loadChih-Min Chao1-6/+10
2020-04-24rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+9
2020-04-20Move vxrm/vxsat from fcsr to vcsrAndrew Waterman1-4/+4
2020-04-09rvv: minor optimization for index load loopChih-Min Chao1-1/+1
2020-04-09rvv: fix index segment load overlapping checkChih-Min Chao1-5/+7
2020-04-09rvv: missing vector enabling check for mask operationChih-Min Chao1-0/+1
2020-03-23rvv: restrict segment load register ruleChih-Min Chao1-3/+1
2020-03-12rvv: commitlog: fix missing dump for some instructionsChih-Min Chao1-4/+4
2020-03-09commitlog: enhance vector dumpChih-Min Chao1-0/+3
2020-03-09rvv: vstart must be 0 for reduction instructionsChih-Min Chao1-0/+1
2020-02-20Debug can actually start at 0x0 nowAndrew Waterman1-2/+1
2020-02-20rvv: only check segment overlapping in index loadChih-Min Chao1-4/+2
2020-02-20rvv: don't zero vstart in the beginningChih-Min Chao1-1/+0
2020-02-18widening reductions are legal when LMUL=8Andrew Waterman1-1/+0
2020-02-18Vector stores don't care if rd overlaps v0 (#400)Andrew Waterman1-9/+16
2020-02-18Merge pull request #396 from chihminchao/rvv-fix-2020-02-14Andrew Waterman1-5/+5
2020-02-18rvv: make variable name match its meaningChih-Min Chao1-1/+1
2020-02-17vadc/vsbc: allow v0 overlap if LMUL = 1Andrew Waterman1-2/+2
2020-02-14rvv: fix exception rethrow in fault-first loadChih-Min Chao1-1/+1
2020-02-14rvv: respect vstart in fault-first loadChih-Min Chao1-3/+3
2020-01-22commitlog: rvv: add commitlog support to integer instructionsChih-Min Chao1-33/+33
2020-01-22commitlog: rvv: add commitlog support to float instrunctionsChih-Min Chao1-11/+11
2020-01-22commitlog: rvv: add commitlog support to load instructionsChih-Min Chao1-8/+9
2020-01-22commitlog: rvv: change vector register read/write interfaceChih-Min Chao1-0/+4
2020-01-22commitlog: extend reg record to keep multiple accesssChih-Min Chao1-2/+2
2020-01-13state: rewrite state_t initializationChih-Min Chao1-0/+8
2020-01-13rvv: segment load/store needs to check destination rangeChih-Min Chao1-2/+3
2020-01-13rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao1-3/+1
2020-01-09rvv: add vfredxxx.vs and vfwred[o]sum.vs float64 supportChih-Min Chao1-12/+28
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