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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-23 20:27:28 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-23 21:53:53 -0700 |
| commit | 5a208b28a23fa408d12f91f838564575a4270043 (patch) | |
| tree | edff7bf568740f04927a4b9c57fee3bd724d503d /riscv/decode.h | |
| parent | f9fbe2205343b5c0cd49f6021eb144e79373959f (diff) | |
| download | riscv-isa-sim-5a208b28a23fa408d12f91f838564575a4270043.zip riscv-isa-sim-5a208b28a23fa408d12f91f838564575a4270043.tar.gz riscv-isa-sim-5a208b28a23fa408d12f91f838564575a4270043.tar.bz2 | |
rvv: restrict segment load register rule
For unit-strided and stride segment load, mask register can't
overlap destination register if masked
ref:
https://github.com/riscv/riscv-v-spec/pull/395
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 1794475..48079c1 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -457,9 +457,8 @@ static inline bool is_overlapped(const int astart, const int asize, #define VI_CHECK_SXX \ VI_CHECK_STORE_SXX; \ - if (P.VU.vlmul > 1 && insn.v_vm() == 0) { \ + if (insn.v_vm() == 0 && (insn.v_nf() > 0 || P.VU.vlmul > 1)) \ require(insn.rd() != 0); \ - } #define VI_CHECK_DSS(is_vs1) \ VI_WIDE_CHECK_COMMON; \ @@ -806,7 +805,6 @@ static inline bool is_overlapped(const int astart, const int asize, // merge and copy loop #define VI_VVXI_MERGE_LOOP(BODY) \ - VI_CHECK_SXX; \ VI_GENERAL_LOOP_BASE \ if (sew == e8){ \ VXI_PARAMS(e8); \ |