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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-13 10:39:34 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-24 00:24:58 -0700 |
| commit | f5be48f027879cc0ff2f3169c09168e5d8d1ffe0 (patch) | |
| tree | 5f92843e51f10fd0e5961c7e909f269bc69354f1 /riscv/decode.h | |
| parent | 81686eae2ee2b7ecdce100c6a424db8e1349ec09 (diff) | |
| download | riscv-isa-sim-f5be48f027879cc0ff2f3169c09168e5d8d1ffe0.zip riscv-isa-sim-f5be48f027879cc0ff2f3169c09168e5d8d1ffe0.tar.gz riscv-isa-sim-f5be48f027879cc0ff2f3169c09168e5d8d1ffe0.tar.bz2 | |
rvv: leave only SEW-bit segment store
new features in spec 0.9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 99de568..56ccc5a 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1486,13 +1486,15 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ } \ } -#define VI_ST_COMMON(stride, offset, st_width, elt_byte) \ +#define VI_ST_COMMON(stride, offset, st_width, elt_byte, is_seg) \ const reg_t nf = insn.v_nf() + 1; \ const reg_t vl = P.VU.vl; \ const reg_t baseAddr = RS1; \ const reg_t vs3 = insn.rd(); \ require((nf * P.VU.vlmul) <= (NVPR / 4) && \ vs3 + nf * P.VU.vlmul <= NVPR); \ + if (!is_seg) \ + require(nf == 1); \ const reg_t vlmul = P.VU.vlmul; \ for (reg_t i = 0; i < vl; ++i) { \ VI_STRIP(i) \ @@ -1563,13 +1565,13 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ if (nf >= 2) \ require(!is_overlapped(vd, nf, insn.rs2(), 1)); -#define VI_ST(stride, offset, st_width, elt_byte) \ +#define VI_ST(stride, offset, st_width, elt_byte, is_seg) \ VI_CHECK_STORE_SXX; \ - VI_ST_COMMON(stride, offset, st_width, elt_byte) \ + VI_ST_COMMON(stride, offset, st_width, elt_byte, is_seg) \ -#define VI_ST_INDEX(stride, offset, st_width, elt_byte) \ +#define VI_ST_INDEX(stride, offset, st_width, elt_byte, is_seg) \ VI_CHECK_ST_INDEX; \ - VI_ST_COMMON(stride, offset, st_width, elt_byte) \ + VI_ST_COMMON(stride, offset, st_width, elt_byte, is_seg) \ #define VI_LDST_FF(itype, tsew, is_seg) \ require(p->VU.vsew >= e##tsew && p->VU.vsew <= e64); \ |