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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-13 01:21:20 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-24 00:24:30 -0700 |
| commit | 7b3d88f5de4e47c989e64d49498233ecda928b09 (patch) | |
| tree | 0c5c09c4d2e927ad3dd13f14fbd5c5b49c010f3e /riscv/decode.h | |
| parent | a261be3dc658e1a483ea6a02733d48be1b70f277 (diff) | |
| download | riscv-isa-sim-7b3d88f5de4e47c989e64d49498233ecda928b09.zip riscv-isa-sim-7b3d88f5de4e47c989e64d49498233ecda928b09.tar.gz riscv-isa-sim-7b3d88f5de4e47c989e64d49498233ecda928b09.tar.bz2 | |
rvv: add vfslide1[down|up].vf and refine checking rule
1. new features in spec 0.9
2. also fix destination commitlog information for integer comparison
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index e1cc414..9855580 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -506,6 +506,15 @@ static inline bool is_overlapped(const int astart, const int asize, require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ require(P.VU.vstart == 0); \ +#define VI_CHECK_SLIDE(is_over) \ + require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ + require((insn.rd() & (P.VU.vlmul - 1)) == 0); \ + if (insn.v_vm() == 0 && P.VU.vlmul > 1) \ + require(insn.rd() != 0); \ + if (is_over) \ + require(insn.rd() != insn.rs2()); \ + + // // vector: loop header and end helper // |