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2019-09-17gdbstub: riscv: fix the fflags registersKONRAD Frederic1-2/+4
2019-09-17target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis1-1/+1
2019-09-17target/riscv: Fix mstatus dirty maskAlistair Francis1-1/+1
2019-09-17target/riscv: Use both register name and ABI nameAtish Patra1-8/+11
2019-09-17riscv: hmp: Add a command to show virtual memory mappingsBin Meng2-0/+233
2019-09-17riscv: rv32: Root page table address can be larger than 32-bitBin Meng1-5/+5
2019-09-17target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis1-17/+18
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis3-10/+26
2019-09-17target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace eventsPhilippe Mathieu-Daudé2-21/+16
2019-09-17target/riscv/pmp: Restrict priviledged PMP to system-mode emulationPhilippe Mathieu-Daudé2-5/+2
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2-6/+6
2019-08-22Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in...Peter Maydell1-1/+1
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster1-1/+1
2019-08-20icount: remove unnecessary gen_io_end callsPavel Dovgalyuk1-1/+0
2019-08-19Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20190819' into stagingPeter Maydell1-18/+1
2019-08-19target/riscv: Remove redundant declaration pragmasRichard Henderson1-18/+1
2019-08-19target/riscv: rationalise softfloat includesAlex Bennée3-1/+3
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing3-1/+18
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt3-0/+8
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt4-0/+9
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis3-5/+14
2019-06-25target/riscv: Remove user version informationAlistair Francis2-25/+9
2019-06-25target/riscv: Require either I or E base extensionAlistair Francis1-0/+6
2019-06-25target/riscv: Set privledge spec 1.11.0 as defaultAlistair Francis1-3/+5
2019-06-25target/riscv: Add the mcountinhibit CSRAlistair Francis2-2/+16
2019-06-24target/riscv: Add the privledge spec version 1.11.0Alistair Francis2-1/+2
2019-06-24target/riscv: Restructure deprecatd CPUsAlistair Francis2-14/+17
2019-06-23RISC-V: Fix a PMP check with the correct access sizeHesham Almatary1-2/+1
2019-06-23RISC-V: Fix a PMP bug where it succeeds even if PMP entry is offHesham Almatary1-4/+5
2019-06-23RISC-V: Check PMP during Page Table WalksHesham Almatary2-1/+10
2019-06-23RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary3-5/+13
2019-06-23RISC-V: Raise access fault exceptions on PMP violationsHesham Almatary1-3/+6
2019-06-23RISC-V: Only Check PMP if MMU translation succeedsHesham Almatary1-0/+1
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark3-0/+19
2019-06-23target/riscv: Fix PMP range boundary address bugDayeol Lee1-1/+1
2019-06-23target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis2-2/+79
2019-06-12Supply missing header guardsMarkus Armbruster3-0/+15
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster3-3/+0
2019-06-11qemu-common: Move qemu_isalnum() etc. to qemu/ctype.hMarkus Armbruster1-0/+1
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-3/+0
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-0/+1
2019-06-10cpu: Introduce cpu_set_cpustate_pointersRichard Henderson1-2/+1
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-2/+0
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson4-21/+13
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-1/+0
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-2/+2
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson2-17/+27
2019-05-24target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens1-1/+3
2019-05-24target/riscv: More accurate handling of `sip` CSRJonathan Behrens1-2/+5