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| author | Markus Armbruster <armbru@redhat.com> | 2019-06-04 20:16:18 +0200 |
|---|---|---|
| committer | Markus Armbruster <armbru@redhat.com> | 2019-06-12 13:20:21 +0200 |
| commit | f91005e195e7e1485e60cb121731589960f1a3c9 (patch) | |
| tree | e734135671b02f0c6bbf5785006401843e925a06 /target/riscv | |
| parent | 37677d7db39a3c250ad661d00fb7c3b59d047b1f (diff) | |
| download | qemu-f91005e195e7e1485e60cb121731589960f1a3c9.zip qemu-f91005e195e7e1485e60cb121731589960f1a3c9.tar.gz qemu-f91005e195e7e1485e60cb121731589960f1a3c9.tar.bz2 | |
Supply missing header guards
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20190604181618.19980-5-armbru@redhat.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_bits.h | 5 | ||||
| -rw-r--r-- | target/riscv/cpu_user.h | 5 | ||||
| -rw-r--r-- | target/riscv/instmap.h | 5 |
3 files changed, 15 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index dc9d53d..47450a3 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -1,5 +1,8 @@ /* RISC-V ISA constants */ +#ifndef TARGET_RISCV_CPU_BITS_H +#define TARGET_RISCV_CPU_BITS_H + #define get_field(reg, mask) (((reg) & \ (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ @@ -527,3 +530,5 @@ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP + +#endif diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h index 52d380a..02afad6 100644 --- a/target/riscv/cpu_user.h +++ b/target/riscv/cpu_user.h @@ -1,3 +1,6 @@ +#ifndef TARGET_RISCV_CPU_USER_H +#define TARGET_RISCV_CPU_USER_H + #define xRA 1 /* return address (aka link register) */ #define xSP 2 /* stack pointer */ #define xGP 3 /* global pointer */ @@ -12,3 +15,5 @@ #define xA6 16 #define xA7 17 /* syscall number for RVI ABI */ #define xT0 5 /* syscall number for RVE ABI */ + +#endif diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index 58baa1b..f8ad7d6 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -16,6 +16,9 @@ * this program. If not, see <http://www.gnu.org/licenses/>. */ +#ifndef TARGET_RISCV_INSTMAP_H +#define TARGET_RISCV_INSTMAP_H + #define MASK_OP_MAJOR(op) (op & 0x7F) enum { /* rv32i, rv64i, rv32m */ @@ -362,3 +365,5 @@ enum { #define GET_C_RS2(inst) extract32(inst, 2, 5) #define GET_C_RS1S(inst) (8 + extract32(inst, 7, 3)) #define GET_C_RS2S(inst) (8 + extract32(inst, 2, 3)) + +#endif |