aboutsummaryrefslogtreecommitdiff
path: root/target/riscv
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2019-03-22 17:16:06 -0700
committerRichard Henderson <richard.henderson@linaro.org>2019-06-10 07:03:42 -0700
commit5b146dc716cfd247f99556c04e6e46fbd67565a0 (patch)
tree7332e8ee9008dd30c402b3167f809677a1f50b4d /target/riscv
parent7506ed902eb97fe4e2a1dd16766c621d32ecc40d (diff)
downloadqemu-5b146dc716cfd247f99556c04e6e46fbd67565a0.zip
qemu-5b146dc716cfd247f99556c04e6e46fbd67565a0.tar.gz
qemu-5b146dc716cfd247f99556c04e6e46fbd67565a0.tar.bz2
cpu: Introduce CPUNegativeOffsetState
Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d9611ea..0ed7031 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -210,6 +210,7 @@ typedef struct RISCVCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPURISCVState env;
/* Configuration Settings */