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authorKONRAD Frederic <frederic.konrad@adacore.com>2019-09-10 10:15:41 +0200
committerPalmer Dabbelt <palmer@sifive.com>2019-09-17 08:42:50 -0700
commitb3e86929189c526d22ef49e18f2f5066535f6deb (patch)
tree51ebc1a0749211c23d2bc131af58bd8b6b6e4deb /target/riscv
parentbdce1a5c6d512257f83b6b6831bee2c975643bbd (diff)
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gdbstub: riscv: fix the fflags registers
While debugging an application with GDB the following might happen: (gdb) return Make xxx return now? (y or n) y Could not fetch register "fflags"; remote failure reply 'E14' This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr number (8). It should use the csr_register_map in order to reach the riscv_cpu_get_fflags callback. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/gdbstub.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 27be932..ded140e 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
+ result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
+ 0, 0);
if (result == 0) {
return gdb_get_regl(mem_buf, val);
}
@@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
+ result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
+ val, -1);
if (result == 0) {
return sizeof(target_ulong);
}