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| author | Alistair Francis <alistair.francis@wdc.com> | 2019-08-23 08:21:22 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:50 -0700 |
| commit | 14115b91ddb106b3e05c74c26a056b253ca666ea (patch) | |
| tree | ac7036c5ff2914eff1b4fcbc6f9b0b473540d1de /target/riscv | |
| parent | a9f37afab111ddbe394574bed5f69683439d46e6 (diff) | |
| download | qemu-14115b91ddb106b3e05c74c26a056b253ca666ea.zip qemu-14115b91ddb106b3e05c74c26a056b253ca666ea.tar.gz qemu-14115b91ddb106b3e05c74c26a056b253ca666ea.tar.bz2 | |
target/riscv: Fix mstatus dirty mask
This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.
Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2789215..f767ad2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -335,7 +335,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) * RV32: MPV and MTL are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |= MSTATUS_MPP | MSTATUS_MPV; + mask |= MSTATUS_MTL | MSTATUS_MPV; #endif } |