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| author | Alistair Francis <alistair.francis@wdc.com> | 2019-06-17 18:31:16 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-06-25 03:05:41 -0700 |
| commit | bdddd44635a7d3b0f746e449ff7a02328bc2b405 (patch) | |
| tree | 8fa05cb9eab93812fe2b161a047d20f354ab7d6a /target/riscv | |
| parent | a101b643c2a74671ffedd50f7a2974937c7a0791 (diff) | |
| download | qemu-bdddd44635a7d3b0f746e449ff7a02328bc2b405.zip qemu-bdddd44635a7d3b0f746e449ff7a02328bc2b405.tar.gz qemu-bdddd44635a7d3b0f746e449ff7a02328bc2b405.tar.bz2 | |
target/riscv: Require either I or E base extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ba1325f..1689ffe 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -373,6 +373,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & cpu->cfg.ext_a & cpu->cfg.ext_f & cpu->cfg.ext_d)) { |