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path: root/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
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13 days[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)Shilei Tian1-10/+12
2025-09-04[AMDGPU] Tail call support for whole wave functions (#145860)Diana Picus1-7/+28
2025-08-15Reapply "[AMDGPU] Intrinsic for launching whole wave functions" (#153584)Diana Picus1-3/+16
2025-08-08[AMDGPU] AsmPrinter: Unify arg handling (#151672)Diana Picus1-0/+12
2025-08-06Revert "[AMDGPU] Intrinsic for launching whole wave functions" (#152286)Diana Picus1-16/+3
2025-08-06[AMDGPU] Intrinsic for launching whole wave functions (#145859)Diana Picus1-3/+16
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus1-3/+29
2025-06-05[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)Diana Picus1-19/+5
2025-05-21Add live in for PrivateSegmentSize in GISel path (#139968)Jake Daly1-0/+6
2025-05-04[Target] Remove unused local variables (NFC) (#138443)Kazu Hirata1-2/+0
2025-03-20[AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (#130094)Diana Picus1-31/+96
2025-02-11[AMDGPU][NFC] Remove an unneeded return value. (#126739)Ivan Kosarev1-9/+10
2024-12-08[AMDGPU] Fix hidden kernarg preload count inconsistency (#116759)Austin Kerbow1-0/+6
2024-11-13[AMDGPU] Remove unused includes (NFC) (#116154)Kazu Hirata1-1/+0
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-3/+1
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-1/+3
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-3/+1
2024-10-30[AMDGPU] Fix @llvm.amdgcn.cs.chain with SGPR args not provably uniform (#114232)Jay Foad1-7/+0
2024-10-04AMDGPU: Do not tail call if an inreg argument requires waterfalling (#111002)Matt Arsenault1-0/+3
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-4/+4
2024-08-13[AMDGPU] Use llvm::any_of, llvm::all_of, and llvm::none_of (NFC) (#103007)Kazu Hirata1-6/+6
2024-07-16[AMDGPU] Fix and add namespace closing comments. NFC.Jay Foad1-1/+1
2024-06-28[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)Nikita Popov1-5/+5
2024-03-26Revert "Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on ...Thomas Symalla1-4/+1
2024-03-21Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets ...SahilPatidar1-1/+4
2024-03-18[GlobalISel] convergence control tokens and intrinsics (#67006)Sameer Sahasrabuddhe1-0/+6
2024-01-21[AMDGPU] Add an asm directive to track code_object_version (#76267)Emma Pilkington1-1/+1
2024-01-17AMDGPU: Allocate special SGPRs before user SGPR arguments (#78234)Matt Arsenault1-6/+5
2024-01-16AMDGPU/GlobalISel: Handle inreg arguments as SGPRs (#78123)Matt Arsenault1-4/+0
2023-11-06[AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (#68186)Diana1-11/+101
2023-10-24[GISel] Make assignValueToReg take CCValAssign by const reference. (#70086)Craig Topper1-3/+3
2023-10-24[GISel] Pass MPO and VA to assignValueToAddress by const reference. NFC (#69810)Craig Topper1-5/+9
2023-09-12[AMDGPU] Add utilities to track number of user SGPRs. NFC.Austin Kerbow1-8/+10
2023-08-20[GlobalISel] introduce MIFlag::NoConvergentSameer Sahasrabuddhe1-0/+3
2023-07-31[GlobalISel] convergent intrinsicsSameer Sahasrabuddhe1-3/+4
2023-07-13[amdgpu][lds] Remove recalculation of LDS frame from backendJon Chesterfield1-4/+0
2023-06-07AMDGPU: Add MF independent version of getImplicitParameterOffsetMatt Arsenault1-1/+1
2023-05-17[CodeGen] Replace CCState's getNextStackOffset with getStackSize (NFC)Sergei Barannikov1-5/+5
2023-04-27AMDGPU: Define sub-class of SGPR_64 for tail call returnChangpeng Fang1-4/+8
2023-02-10AMDGPU: Use module flag to get code object version at IR level folow-upChangpeng Fang1-1/+2
2023-02-02AMDGPU: Use module flag to get code object version at IR levelChangpeng Fang1-1/+2
2023-01-28[Target] Use llvm::count{l,r}_{zero,one} (NFC)Kazu Hirata1-1/+1
2023-01-18Drop the ZeroBehavior parameter from countLeadingZeros and the like (NFC)Kazu Hirata1-2/+1
2022-12-17std::optional::value => operator*/operator->Fangrui Song1-2/+2
2022-12-15AMDGPU/GlobalISel: Do not create readfirstlane with non-s32 typeMatt Arsenault1-0/+12
2022-12-13[CodeGen] llvm::Optional => std::optionalFangrui Song1-1/+1
2022-12-02[Target] Use std::nullopt instead of None (NFC)Kazu Hirata1-1/+1
2022-09-28[amdgpu][nfc] Allocate kernel-specific LDS struct deterministicallyJon Chesterfield1-2/+2
2022-07-19Use value instead of getValue (NFC)Kazu Hirata1-1/+1
2022-07-19Use has_value instead of hasValue (NFC)Kazu Hirata1-1/+1
generated by cgit v1.1 at 2025-09-29 13:10:07 +0000