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author | Craig Topper <craig.topper@sifive.com> | 2023-10-24 15:47:04 -0700 |
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committer | GitHub <noreply@github.com> | 2023-10-24 15:47:04 -0700 |
commit | 2f4328e6979004fbf531d69a40c2e06d43d3128c (patch) | |
tree | 782a044f2d47013fe5dd932581b1b2ce41b445aa /llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | |
parent | b4e552999de518a1d006c7b84f94491beeb4092c (diff) | |
download | llvm-2f4328e6979004fbf531d69a40c2e06d43d3128c.zip llvm-2f4328e6979004fbf531d69a40c2e06d43d3128c.tar.gz llvm-2f4328e6979004fbf531d69a40c2e06d43d3128c.tar.bz2 |
[GISel] Make assignValueToReg take CCValAssign by const reference. (#70086)
This was previously passed by value. It used to be passed by non-const
reference, but it was changed to value in D110610. I'm not sure why.
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp index 08bce3b..bc5f170 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -62,7 +62,7 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); // If this is a scalar return, insert a readfirstlane just in case the value @@ -118,7 +118,7 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { markPhysRegUsed(PhysReg); if (VA.getLocVT().getSizeInBits() < 32) { @@ -231,7 +231,7 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler { } void assignValueToReg(Register ValVReg, Register PhysReg, - CCValAssign VA) override { + const CCValAssign &VA) override { MIB.addUse(PhysReg, RegState::Implicit); Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); |