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2024-06-06opcodes/riscv: prevent future use of disassemble_info::fprintf_funcAndrew Burgess1-0/+5
2024-06-06opcodes/riscv: add styling support to print_reg_listAndrew Burgess1-14/+37
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng1-0/+4
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng1-0/+4
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng1-0/+5
2024-06-05arm: remove disassembly support for the FPA co-processorRichard Earnshaw1-196/+1
2024-06-05Fix illegal memory access when bfd_get_section_contents is called with a NULL...Nick Clifton1-0/+7
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett1-0/+26
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett2-0/+8
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+3
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich4-5657/+5662
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com6-130/+252
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com10-362/+509
2024-05-28opcodes: add a .gitattributes file for aarch64 autogenerated file exceptionsRichard Earnshaw1-0/+3
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich2-16/+16
2024-05-22aarch64: fix incorrect encoding for system register pmsdsfr_el1Matthieu Longo1-1/+1
2024-05-22Support APX zero-upperCui, Lili8-6243/+6985
2024-05-21aarch64: Fix the hyphenated disassembly comment.Srinath Parvathaneni1-2/+2
2024-05-20aarch64: Add support for the fpmr system registerClaudio Bantaloukas1-0/+1
2024-05-17aarch64: correct SVE2.1 ld2q (scalar plus scalar)Jan Beulich2-12/+21
2024-05-17aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate)Jan Beulich1-4/+4
2024-05-16aarch64: fp8 convert and scale - add sme2 insn variantsVictor Do Nascimento2-136/+328
2024-05-16aarch64: fp8 convert and scale - add sve2 insn variantsVictor Do Nascimento2-31/+183
2024-05-16aarch64: fp8 convert and scale - Add advsimd insn variantsVictor Do Nascimento2-36/+220
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento1-0/+18
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo1-0/+4
2024-05-15RISC-V: Search for mapping symbols from the last one foundJoseph Faulls1-8/+4
2024-05-14arm: opcodes: remove Maverick disassembly.Richard Earnshaw1-178/+1
2024-05-08RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu1-88/+88
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili2-115/+117
2024-05-06x86: Drop SwapSourcesCui, Lili3-319/+319
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili3-655/+657
2024-05-03x86: tidy <sse*> templatesJan Beulich1-20/+20
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich2-230/+261
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich2-653/+1987
2024-05-03x86: zap value-less Disp8MemShift from non-EVEX templatesJan Beulich1-7/+19
2024-04-23arm: Fix MVE vmla encodingClaudio Bantaloukas1-1/+1
2024-04-22aarch64: Fix coding style issue in `aarch64-dis.c'Victor Do Nascimento1-1/+1
2024-04-22x86/APX: Add invalid check for APX EVEX.X4.Cui, Lili1-0/+3
2024-04-19mmix disassemble memory leakAlan Modra1-0/+1
2024-04-17aarch64: Remove asserts from operand qualifier decoders [PR31595]Victor Do Nascimento1-18/+80
2024-04-17Add W table for USER_MSR under MAP4.Hu, Lin14-3/+13
2024-04-09aarch64: Treat operand "SME list of ZA tiles" as immediate (PR 31561)Jens Remus1-1/+1
2024-04-09s390: Flag conditional branch relative insns as condjumpJens Remus1-4/+4
2024-04-09arm: Fix disassembly of MVE vq[r]shr[u]nAlex Coplan1-0/+4
2024-04-09arm: Refactor condition for print_mve_shift_nAlex Coplan1-10/+25
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei2-0/+71
2024-04-09Support {evex} pseudo prefix for decode evex promoted insns without egpr32.Hu, Lin12-42/+74
2024-04-07Support APX NFCui, Lili7-397/+825
2024-04-06Revert "x86: Restore APX shift-double instructions with omitted shift count"H.J. Lu2-309/+284