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| author | Alex Coplan <alex.coplan@arm.com> | 2024-04-02 14:27:58 +0100 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2024-04-09 10:09:25 +0100 |
| commit | cd714ac07cbe6a9206df3bc81607818b272399f9 (patch) | |
| tree | af6f7ac3bf686e1e35970d1935f1dd649428a76a /opcodes | |
| parent | b3a561abc3040264aa0c60a8082e2433b0ca38a1 (diff) | |
| download | gdb-cd714ac07cbe6a9206df3bc81607818b272399f9.zip gdb-cd714ac07cbe6a9206df3bc81607818b272399f9.tar.gz gdb-cd714ac07cbe6a9206df3bc81607818b272399f9.tar.bz2 | |
arm: Fix disassembly of MVE vq[r]shr[u]n
This patch fixes the disassembly of vq[r]shr[u]n insns so that the
shift immediate is properly decoded. See the description of the
previous patch for an example of the incorrect disassembly.
As part of this patch we also fix the mve-vqrshrn.d test which was
testing for the incorrect disassembly of the immediates. The
disassembly now matches the assembled instructions in that test.
Finally we add an mve-vqshrn test which tests the non-rounding variants
of those insns, whose encoding we fixed with the previous patch in this
series.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/arm-dis.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index ac5fb92..6550cf4 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -7975,6 +7975,10 @@ mve_shift_insn_p (enum mve_instructions insn) { case MVE_VQSHL_T2: case MVE_VQSHLU_T3: + case MVE_VQSHRN: + case MVE_VQSHRUN: + case MVE_VQRSHRN: + case MVE_VQRSHRUN: case MVE_VRSHR: case MVE_VRSHRN: case MVE_VSHL_T1: |