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authorVictor Do Nascimento <vicdon01@e133397.arm.com>2024-02-27 01:32:52 +0000
committerVictor Do Nascimento <victor.donascimento@arm.com>2024-05-16 13:22:30 +0100
commiteef66d27fcdc55c83a63a17f295409bb4a13688b (patch)
treeb9365975ccffe8a10e988a0bd7c409a6a5002926 /opcodes
parentab501c0deebc13c037f5385749b67d5186253e05 (diff)
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aarch64: fp8 convert and scale - add sve2 insn variants
Add the SVE2 variant of the FP8 convert and scale instructions, enabled at assembly-time using the `+sve2+fp8' architectural extension flag. More specifically, support is added for the following instructions: FP8 convert to BFloat16 (bottom/top): ------------------------------------- - bf1cvt Z<d>.H, Z<n>.B - bf2cvt Z<d>.H, Z<n>.B - bf1cvtlt Z<d>.H, Z<n>.B - bf2cvtlt Z<d>.H, Z<n>.B FP8 convert to half-precision (bottom/top): ------------------------------------------- - f1cvt Z<d>.H, Z<n>.B - f2cvt Z<d>.H, Z<n>.B - f1cvtlt Z<d>.H, Z<n>.B - f2cvtlt Z<d>.H, Z<n>.B BFloat16/half-precision convert, narrow and interleave to FP8: ------------------------------------------- - bfcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H } - fcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H } Single-precision convert, narrow and interleave to FP8 (bottom/top): ----------------------------------------------- - fcvtnb Z<d>.B, { Z<n>1.S - Z<n>2.S } - fcvtnt Z<d>.B, { Z<n>1.S - Z<n>2.S }
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/aarch64-dis-2.c194
-rw-r--r--opcodes/aarch64-tbl.h20
2 files changed, 183 insertions, 31 deletions
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 2268bf6..36d4744 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -10334,7 +10334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3346;
+ return 3358;
}
else
{
@@ -10342,7 +10342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3347;
+ return 3359;
}
}
}
@@ -11260,7 +11260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3348;
+ return 3360;
}
else
{
@@ -11268,7 +11268,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3349;
+ return 3361;
}
}
}
@@ -11353,7 +11353,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3350;
+ return 3362;
}
else
{
@@ -11460,7 +11460,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3352;
+ return 3364;
}
else
{
@@ -11665,7 +11665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3351;
+ return 3363;
}
else
{
@@ -11706,7 +11706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3353;
+ return 3365;
}
else
{
@@ -13364,7 +13364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3355;
+ return 3367;
}
}
else
@@ -13394,7 +13394,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3354;
+ return 3366;
}
}
}
@@ -20817,11 +20817,55 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0x1000001xxxxxxxxxxxxx
- fadda. */
- return 1447;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx001000001x00xxxxxxxxxx
+ f1cvt. */
+ return 3350;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx001000001x10xxxxxxxxxx
+ bf1cvt. */
+ return 3346;
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx001000001x01xxxxxxxxxx
+ f2cvt. */
+ return 3351;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx001000001x11xxxxxxxxxx
+ bf2cvt. */
+ return 3347;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx011000001xxxxxxxxxxxxx
+ fadda. */
+ return 1447;
+ }
}
}
else
@@ -20837,11 +20881,55 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 18) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0xx010001xxxxxxxxxxxxx
- fcmeq. */
- return 1453;
+ if (((word >> 19) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x0010001xxxxxxxxxxxxx
+ fcmeq. */
+ return 1453;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1010001x00xxxxxxxxxx
+ fcvtn. */
+ return 3355;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1010001x10xxxxxxxxxx
+ bfcvtn. */
+ return 3354;
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1010001x01xxxxxxxxxx
+ fcvtnb. */
+ return 3356;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1010001x11xxxxxxxxxx
+ fcvtnt. */
+ return 3357;
+ }
+ }
+ }
}
else
{
@@ -20870,21 +20958,65 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 18) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0xx001001xxxxxxxx0xxxx
- fcmlt. */
- return 1460;
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x0001001xxxxxxxx0xxxx
+ fcmlt. */
+ return 1460;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x0001001xxxxxxxx1xxxx
+ fcmle. */
+ return 1459;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0xx001001xxxxxxxx1xxxx
- fcmle. */
- return 1459;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1001001x00xxxxxxxxxx
+ f1cvtlt. */
+ return 3352;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1001001x10xxxxxxxxxx
+ bf1cvtlt. */
+ return 3348;
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1001001x01xxxxxxxxxx
+ f2cvtlt. */
+ return 3353;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1001001x11xxxxxxxxxx
+ bf2cvtlt. */
+ return 3349;
+ }
+ }
}
}
else
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index f876c1b..464d931 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1644,6 +1644,14 @@
{ \
QLF2(S_H,S_B), \
}
+#define OP_SVE_BH \
+{ \
+ QLF2(S_B,S_H), \
+}
+#define OP_SVE_BS \
+{ \
+ QLF2(S_B,S_S), \
+}
#define OP_SVE_HHH \
{ \
QLF3(S_H,S_H,S_H), \
@@ -6500,6 +6508,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
FP8_INSN("fcvtn", 0xe40f400, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_V3_BHH, F_SIZEQ),
FP8_INSN("fscale", 0x2ec03c00, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_VSHIFT_H, F_SIZEQ),
FP8_INSN("fscale", 0x2ea0fc00, 0xbfa0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ FP8_SVE2_INSN ("bf1cvt", 0x65083800, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("bf2cvt", 0x65083c00, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("bf1cvtlt", 0x65093800, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("bf2cvtlt", 0x65093c00, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("f1cvt", 0x65083000, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("f2cvt", 0x65083400, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("f1cvtlt", 0x65093000, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("f2cvtlt", 0x65093400, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("bfcvtn", 0x650a3800, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
+ FP8_SVE2_INSN ("fcvtn", 0x650a3000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
+ FP8_SVE2_INSN ("fcvtnb", 0x650a3400, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BS, 0, 0),
+ FP8_SVE2_INSN ("fcvtnt", 0x650a3c00, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BS, 0, 0),
/* Checked Pointer Arithmetic Instructions. */
CPA_INSN ("addpt", 0x9a002000, 0xffe0e000, aarch64_misc, OP3 (Rd_SP, Rn_SP, Rm_LSL), QL_I3SAMEX),