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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2024-06-06 15:59:52 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-06 16:10:51 +0800 |
| commit | d9c14a8744b01b0d3d03a661c732a4d4d5740fbc (patch) | |
| tree | 104016466320290c6444f5b089e737449cf23f7d /opcodes | |
| parent | af38c6367ff0c6af1639b389eb34cf9983c30ff5 (diff) | |
| download | gdb-d9c14a8744b01b0d3d03a661c732a4d4d5740fbc.zip gdb-d9c14a8744b01b0d3d03a661c732a4d4d5740fbc.tar.gz gdb-d9c14a8744b01b0d3d03a661c732a4d4d5740fbc.tar.bz2 | |
RISC-V: Add support for Zvfbfmin extension
This implements the Zvfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts>
Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.
For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvfbfmin.d: New test.
* testsuite/gas/riscv/zvfbfmin.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
(MASK_VFNCVTBF16_F_F_W): Ditto.
(MATCH_VFWCVTBF16_F_F_V): Ditto.
(MASK_VFWCVTBF16_F_F_V): Ditto.
(DECLARE_INSN): New declarations for Zvfbfmin.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZVFBFMIN
opcodes/ChangeLog:
* riscv-opc.c: Add Zvfbfmin instructions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 1ccf068..eccd3f6 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2017,6 +2017,10 @@ const struct riscv_opcode riscv_opcodes[] = {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0}, {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0}, +/* Zvfbfmin instructions. */ +{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0}, +{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0}, + /* Zvbb/Zvkb instructions. */ {"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0}, {"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0}, |