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| author | Mary Bennett <mary.bennett682@gmail.com> | 2024-05-30 16:06:57 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-05 18:09:09 +0800 |
| commit | 940da069b48980ce957dd4cc010a9a41e05d1553 (patch) | |
| tree | b259f1aeefe9dcafcb45ee0d8497602aa288b03a /opcodes | |
| parent | f95540d91f4c3df373c0f9e212030154658d7f6f (diff) | |
| download | gdb-940da069b48980ce957dd4cc010a9a41e05d1553.zip gdb-940da069b48980ce957dd4cc010a9a41e05d1553.tar.gz gdb-940da069b48980ce957dd4cc010a9a41e05d1553.tar.bz2 | |
RISC-V: Add support for XCVelw extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction
class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XCVelw as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-elw-fail.d: New test.
* testsuite/gas/riscv/cv-elw-fail.l: New test.
* testsuite/gas/riscv/cv-elw-fail.s: New test.
* testsuite/gas/riscv/cv-elw-fail-march.d: New test.
* testsuite/gas/riscv/cv-elw-fail-march.l: New test.
* testsuite/gas/riscv/cv-elw-fail-march.s: New test.
* testsuite/gas/riscv/cv-elw-pass.d: New test.
* testsuite/gas/riscv/cv-elw-pass.s: New test.
* testsuite/gas/riscv/march-help.l: Add xcvelw string.
opcodes/ChangeLog:
* riscv-opc.c: (riscv_opcode) Add event load instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK
instruction opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 1ef4ead..42fb44f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2207,6 +2207,9 @@ const struct riscv_opcode riscv_opcodes[] = {"cv.subrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBRNR, MASK_CV_SUBRNR, match_opcode, 0}, {"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBURNR, MASK_CV_SUBURNR, match_opcode, 0}, +/* Vendor-specific (CORE-V) Xcvelw instructions. */ +{"cv.elw", 0, INSN_CLASS_XCVELW, "d,o(s)", MATCH_CV_ELW, MASK_CV_ELW, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadBa instructions. */ {"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0}, |