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2019-01-05RX: include - Add RXv3 support.Yoshinori Sato3-1/+43
2019-01-01Update year range in copyright notice of binutils filesAlan Modra284-283/+287
2019-01-01ChangeLog rotationAlan Modra2-878/+892
2019-01-01Update copyright year range in all GDB files.Joel Brobecker22-22/+22
2018-12-28PR24028, PPC_INT_FMTAlan Modra2-8/+5
2018-12-14elf: Add PT_GNU_PROPERTY segment typeH.J. Lu2-3/+7
2018-12-11Fix a failure in the libiberty testsuite by increasing the recursion limit to...Nick Clifton2-1/+6
2018-12-07elf: Report property change when merging propertiesH.J. Lu2-0/+7
2018-12-07Synchronize libiberty with gcc and add --no-recruse-limit option to tools tha...Nick Clifton2-0/+19
2018-12-06PowerPC @l, @h and @ha warnings, plus VLE e_liAlan Modra2-0/+9
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess3-0/+13
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson2-1/+6
2018-11-27RISC-V: Add .insn CA support.Jim Wilson2-0/+9
2018-11-13[ARM] Improve indentation of ARM architecture declarationsThomas Preud'homme2-254/+340
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das2-0/+7
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das2-0/+14
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das2-0/+7
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das2-0/+6
2018-11-07Add support for new load commands added by Apple to the MACH-O file format.Roman Bolshakov3-28/+55
2018-11-06Add support for a couple of new Mach-O commands.Nick Clifton2-1/+7
2018-11-06[BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros.Sudakshina Das2-4/+9
2018-10-26Support AT_HWCAP2 on FreeBSD.John Baldwin2-0/+5
2018-10-23S12Z: New 32 bit Reloc.John Darrington1-1/+2
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das2-1/+9
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das2-1/+14
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das2-1/+21
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das2-0/+6
2018-10-09[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das2-1/+8
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das2-1/+13
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das2-1/+9
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das2-1/+14
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das2-0/+9
2018-10-08Separate header PT_LOAD for -z separate-codeAlan Modra2-0/+7
2018-10-05[Arm, 3/3] Add Execution and Data Prediction instructions for AArch32Sudakshina Das2-1/+8
2018-10-05[Arm, 2/3] Add instruction SB for AArch32Sudakshina Das2-1/+8
2018-10-05[Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32Sudakshina Das2-0/+10
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne2-0/+20
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson2-0/+13
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina2-2/+16
2018-10-03AArch64: Refactor verifiers to make more general.Tamar Christina2-1/+8
2018-10-03AArch64: Refactor err_type.Tamar Christina2-1/+16
2018-10-03AArch64: Wire through instr_sequenceTamar Christina2-2/+27
2018-10-03AArch64: Mark sve instructions that require MOVPRFX constraintsTamar Christina2-2/+22
2018-10-03Make print_insn_s12z public.John Darrington2-0/+5
2018-10-02RISC-V: Add fence.tso instructionPalmer Dabbelt2-0/+7
2018-10-02[ARC] Entries to Changelog for previous commits.Cupertino Miranda1-0/+4
2018-10-01[ARC] Fixed issue with DTSOFF relocs.Cupertino Miranda1-1/+1
2018-10-01[ARC] Fixes TLS failures related to tls-align.Cupertino Miranda1-1/+1
2018-09-21ELF: Don't include zero size sections at start of PT_NOTE segmentH.J. Lu2-4/+12
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton4-43/+240
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