diff options
| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 11:04:32 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:39:29 +0100 |
| commit | 104fefeebb544b7745bb353b63110afa46119647 (patch) | |
| tree | 64540070841260d12abe4b232e89eb208ac77869 /include | |
| parent | a97330e723cf3c639a951329ac5fe2797528249b (diff) | |
| download | gdb-104fefeebb544b7745bb353b63110afa46119647.zip gdb-104fefeebb544b7745bb353b63110afa46119647.tar.gz gdb-104fefeebb544b7745bb353b63110afa46119647.tar.bz2 | |
[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds support for the mitigation for Spectre Variant 4 by
adding the PSTATE bit SSBS which are accessible using MSR and MRS
instructions. Although this is a mandatory addition to the ARMv8.5-A,
it is permitted to be added to any version of the ARMv8 architecture.
This is enabled using the command line option of +ssbs for older
versions.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Add
SSBS in the check for one-bit immediate.
(aarch64_sys_regs): New entry for SSBS.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for SSBS.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "ssbs".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/ssbs-illegal1.d: New test.
* testsuite/gas/aarch64/ssbs-illegal1.l: New test.
* testsuite/gas/aarch64/ssbs-illegal2.d: New test.
* testsuite/gas/aarch64/ssbs-illegal2.l: New test.
* testsuite/gas/aarch64/ssbs.s: New test.
* testsuite/gas/aarch64/ssbs1.d: Test with +ssbs
* testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 5 |
2 files changed, 9 insertions, 1 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index ed5dcf2..0c692ee 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,10 @@ 2018-10-09 Sudakshina Das <sudi.das@arm.com> + * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New. + (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default. + +2018-10-09 Sudakshina Das <sudi.das@arm.com> + * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New. (AARCH64_FEATURE_ID_PFR2): New. (AARCH64_ARCH_V8_5): Add both by default. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index b56f907..8487767 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -82,6 +82,8 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL /* ID_PFR2 instructions. */ #define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL +/* SSBS mechanism enabled. */ +#define AARCH64_FEATURE_SSBS 0x800000000000ULL /* Architectures are the sum of the base and extensions. */ @@ -115,7 +117,8 @@ typedef uint32_t aarch64_insn; | AARCH64_FEATURE_CVADP \ | AARCH64_FEATURE_BTI \ | AARCH64_FEATURE_SCXTNUM \ - | AARCH64_FEATURE_ID_PFR2) + | AARCH64_FEATURE_ID_PFR2 \ + | AARCH64_FEATURE_SSBS) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) |